Added MSA optimized transform functions
1. TransformWHT 2. TransformTwo 3. TransformDC 4. TransformAC3 Change-Id: Ia3624cb4aed215bcaffce542b28794e643207039
This commit is contained in:
Parag Salasakar
parent
4c59aac0f9
commit
5e60c42a76
@ -49,6 +49,7 @@ dsp_dec_srcs := \
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src/dsp/dec_clip_tables.c \
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src/dsp/dec_mips32.c \
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src/dsp/dec_mips_dsp_r2.c \
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src/dsp/dec_msa.c \
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src/dsp/dec_neon.$(NEON) \
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src/dsp/dec_sse2.c \
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src/dsp/dec_sse41.c \
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@ -194,6 +194,7 @@ DSP_DEC_OBJS = \
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$(DIROBJ)\dsp\dec_clip_tables.obj \
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$(DIROBJ)\dsp\dec_mips32.obj \
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$(DIROBJ)\dsp\dec_mips_dsp_r2.obj \
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$(DIROBJ)\dsp\dec_msa.obj \
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$(DIROBJ)\dsp\dec_neon.obj \
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$(DIROBJ)\dsp\dec_sse2.obj \
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$(DIROBJ)\dsp\dec_sse41.obj \
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@ -38,12 +38,20 @@ model {
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architecture "x86_64"
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}
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mips32r2
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mips32r5
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mips64r6
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}
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toolChains {
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gcc(Gcc) {
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target("mips32r2") {
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cCompiler.args "-mips32r2"
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}
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target("mips32r5") {
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cCompiler.args "-mips32r5"
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}
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target("mips64r6") {
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cCompiler.args "-mips64r6"
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}
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}
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}
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binaries {
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@ -111,6 +119,7 @@ model {
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include "dec_clip_tables.c"
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include "dec_mips32.c"
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include "dec_mips_dsp_r2.c"
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include "dec_msa.c"
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include "dec_neon.$NEON"
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include "dec_sse2.c"
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include "dec_sse41.c"
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@ -138,6 +138,7 @@ DSP_DEC_OBJS = \
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src/dsp/dec_clip_tables.o \
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src/dsp/dec_mips32.o \
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src/dsp/dec_mips_dsp_r2.o \
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src/dsp/dec_msa.o \
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src/dsp/dec_neon.o \
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src/dsp/dec_sse2.o \
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src/dsp/dec_sse41.o \
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@ -273,6 +274,7 @@ HDRS = \
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src/dsp/dsp.h \
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src/dsp/lossless.h \
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src/dsp/mips_macro.h \
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src/dsp/msa_macro.h \
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src/dsp/neon.h \
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src/dsp/yuv.h \
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src/enc/backward_references.h \
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@ -2,6 +2,7 @@ noinst_LTLIBRARIES = libwebpdsp.la libwebpdsp_avx2.la
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noinst_LTLIBRARIES += libwebpdsp_sse2.la libwebpdspdecode_sse2.la
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noinst_LTLIBRARIES += libwebpdsp_sse41.la libwebpdspdecode_sse41.la
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noinst_LTLIBRARIES += libwebpdsp_neon.la libwebpdspdecode_neon.la
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noinst_LTLIBRARIES += libwebpdspdecode_msa.la
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if BUILD_LIBWEBPDECODER
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noinst_LTLIBRARIES += libwebpdspdecode.la
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@ -80,6 +81,12 @@ libwebpdspdecode_neon_la_SOURCES += upsampling_neon.c
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libwebpdspdecode_neon_la_CPPFLAGS = $(libwebpdsp_neon_la_CPPFLAGS)
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libwebpdspdecode_neon_la_CFLAGS = $(libwebpdsp_neon_la_CFLAGS)
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libwebpdspdecode_msa_la_SOURCES =
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libwebpdspdecode_msa_la_SOURCES += dec_msa.c
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libwebpdspdecode_msa_la_SOURCES += msa_macro.h
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libwebpdspdecode_msa_la_CPPFLAGS = $(libwebpdsp_la_CPPFLAGS)
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libwebpdspdecode_msa_la_CFLAGS = $(AM_CFLAGS)
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libwebpdsp_sse2_la_SOURCES =
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libwebpdsp_sse2_la_SOURCES += argb_sse2.c
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libwebpdsp_sse2_la_SOURCES += cost_sse2.c
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@ -117,6 +124,7 @@ libwebpdsp_la_LIBADD =
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libwebpdsp_la_LIBADD += libwebpdsp_avx2.la libwebpdsp_sse2.la
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libwebpdsp_la_LIBADD += libwebpdsp_sse41.la
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libwebpdsp_la_LIBADD += libwebpdsp_neon.la
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libwebpdsp_la_LIBADD += libwebpdspdecode_msa.la
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if BUILD_LIBWEBPDECODER
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libwebpdspdecode_la_SOURCES = $(COMMON_SOURCES)
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@ -127,4 +135,5 @@ if BUILD_LIBWEBPDECODER
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libwebpdspdecode_la_LIBADD += libwebpdspdecode_sse2.la
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libwebpdspdecode_la_LIBADD += libwebpdspdecode_sse41.la
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libwebpdspdecode_la_LIBADD += libwebpdspdecode_neon.la
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libwebpdspdecode_la_LIBADD += libwebpdspdecode_msa.la
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endif
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@ -699,6 +699,7 @@ extern void VP8DspInitSSE41(void);
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extern void VP8DspInitNEON(void);
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extern void VP8DspInitMIPS32(void);
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extern void VP8DspInitMIPSdspR2(void);
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extern void VP8DspInitMSA(void);
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static volatile VP8CPUInfo dec_last_cpuinfo_used =
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(VP8CPUInfo)&dec_last_cpuinfo_used;
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@ -783,6 +784,11 @@ WEBP_TSAN_IGNORE_FUNCTION void VP8DspInit(void) {
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if (VP8GetCPUInfo(kMIPSdspR2)) {
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VP8DspInitMIPSdspR2();
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}
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#endif
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#if defined(WEBP_USE_MSA)
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if (VP8GetCPUInfo(kMSA)) {
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VP8DspInitMSA();
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}
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#endif
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}
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dec_last_cpuinfo_used = VP8GetCPUInfo;
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172
src/dsp/dec_msa.c
Normal file
172
src/dsp/dec_msa.c
Normal file
@ -0,0 +1,172 @@
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// Copyright 2016 Google Inc. All Rights Reserved.
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//
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// Use of this source code is governed by a BSD-style license
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// that can be found in the COPYING file in the root of the source
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// tree. An additional intellectual property rights grant can be found
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// in the file PATENTS. All contributing project authors may
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// be found in the AUTHORS file in the root of the source tree.
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// -----------------------------------------------------------------------------
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//
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// MSA version of dsp functions
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//
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// Author(s): Prashant Patil (prashant.patil@imgtec.com)
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#include "./dsp.h"
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#if defined(WEBP_USE_MSA)
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#include "./msa_macro.h"
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//------------------------------------------------------------------------------
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// Transforms
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#define IDCT_1D_W(in0, in1, in2, in3, out0, out1, out2, out3) { \
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v4i32 a1_m, b1_m, c1_m, d1_m; \
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v4i32 c_tmp1_m, c_tmp2_m, d_tmp1_m, d_tmp2_m; \
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const v4i32 cospi8sqrt2minus1 = __msa_fill_w(20091); \
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const v4i32 sinpi8sqrt2 = __msa_fill_w(35468); \
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\
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a1_m = in0 + in2; \
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b1_m = in0 - in2; \
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c_tmp1_m = (in1 * sinpi8sqrt2) >> 16; \
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c_tmp2_m = in3 + ((in3 * cospi8sqrt2minus1) >> 16); \
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c1_m = c_tmp1_m - c_tmp2_m; \
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d_tmp1_m = in1 + ((in1 * cospi8sqrt2minus1) >> 16); \
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d_tmp2_m = (in3 * sinpi8sqrt2) >> 16; \
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d1_m = d_tmp1_m + d_tmp2_m; \
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BUTTERFLY_4(a1_m, b1_m, c1_m, d1_m, out0, out1, out2, out3); \
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}
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#define MULT1(a) ((((a) * 20091) >> 16) + (a))
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#define MULT2(a) (((a) * 35468) >> 16)
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static void TransformOne(const int16_t* in, uint8_t* dst) {
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v8i16 input0, input1;
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v4i32 in0, in1, in2, in3, hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3;
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v4i32 res0, res1, res2, res3;
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const v16i8 zero = { 0 };
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v16i8 dest0, dest1, dest2, dest3;
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LD_SH2(in, 8, input0, input1);
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UNPCK_SH_SW(input0, in0, in1);
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UNPCK_SH_SW(input1, in2, in3);
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IDCT_1D_W(in0, in1, in2, in3, hz0, hz1, hz2, hz3);
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TRANSPOSE4x4_SW_SW(hz0, hz1, hz2, hz3, hz0, hz1, hz2, hz3);
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IDCT_1D_W(hz0, hz1, hz2, hz3, vt0, vt1, vt2, vt3);
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SRARI_W4_SW(vt0, vt1, vt2, vt3, 3);
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TRANSPOSE4x4_SW_SW(vt0, vt1, vt2, vt3, vt0, vt1, vt2, vt3);
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LD_SB4(dst, BPS, dest0, dest1, dest2, dest3);
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ILVR_B4_SW(zero, dest0, zero, dest1, zero, dest2, zero, dest3,
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res0, res1, res2, res3);
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ILVR_H4_SW(zero, res0, zero, res1, zero, res2, zero, res3,
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res0, res1, res2, res3);
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ADD4(res0, vt0, res1, vt1, res2, vt2, res3, vt3, res0, res1, res2, res3);
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CLIP_SW4_0_255(res0, res1, res2, res3);
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PCKEV_B2_SW(res0, res1, res2, res3, vt0, vt1);
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res0 = (v4i32)__msa_pckev_b((v16i8)vt0, (v16i8)vt1);
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ST4x4_UB(res0, res0, 3, 2, 1, 0, dst, BPS);
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}
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static void TransformTwo(const int16_t* in, uint8_t* dst, int do_two) {
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TransformOne(in, dst);
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if (do_two) {
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TransformOne(in + 16, dst + 4);
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}
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}
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static void TransformWHT(const int16_t* in, int16_t* out) {
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v8i16 input0, input1;
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const v8i16 mask0 = { 0, 1, 2, 3, 8, 9, 10, 11 };
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const v8i16 mask1 = { 4, 5, 6, 7, 12, 13, 14, 15 };
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const v8i16 mask2 = { 0, 4, 8, 12, 1, 5, 9, 13 };
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const v8i16 mask3 = { 3, 7, 11, 15, 2, 6, 10, 14 };
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v8i16 tmp0, tmp1, tmp2, tmp3;
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v8i16 out0, out1;
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LD_SH2(in, 8, input0, input1);
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input1 = SLDI_SH(input1, input1, 8);
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tmp0 = input0 + input1;
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tmp1 = input0 - input1;
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VSHF_H2_SH(tmp0, tmp1, tmp0, tmp1, mask0, mask1, tmp2, tmp3);
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out0 = tmp2 + tmp3;
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out1 = tmp2 - tmp3;
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VSHF_H2_SH(out0, out1, out0, out1, mask2, mask3, input0, input1);
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tmp0 = input0 + input1;
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tmp1 = input0 - input1;
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VSHF_H2_SH(tmp0, tmp1, tmp0, tmp1, mask0, mask1, tmp2, tmp3);
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tmp0 = tmp2 + tmp3;
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tmp1 = tmp2 - tmp3;
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ADDVI_H2_SH(tmp0, 3, tmp1, 3, out0, out1);
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SRAI_H2_SH(out0, out1, 3);
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out[0] = __msa_copy_s_h(out0, 0);
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out[16] = __msa_copy_s_h(out0, 4);
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out[32] = __msa_copy_s_h(out1, 0);
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out[48] = __msa_copy_s_h(out1, 4);
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out[64] = __msa_copy_s_h(out0, 1);
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out[80] = __msa_copy_s_h(out0, 5);
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out[96] = __msa_copy_s_h(out1, 1);
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out[112] = __msa_copy_s_h(out1, 5);
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out[128] = __msa_copy_s_h(out0, 2);
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out[144] = __msa_copy_s_h(out0, 6);
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out[160] = __msa_copy_s_h(out1, 2);
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out[176] = __msa_copy_s_h(out1, 6);
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out[192] = __msa_copy_s_h(out0, 3);
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out[208] = __msa_copy_s_h(out0, 7);
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out[224] = __msa_copy_s_h(out1, 3);
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out[240] = __msa_copy_s_h(out1, 7);
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}
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static void TransformDC(const int16_t* in, uint8_t* dst) {
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const int DC = (in[0] + 4) >> 3;
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const v8i16 tmp0 = __msa_fill_h(DC);
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ADDBLK_ST4x4_UB(tmp0, tmp0, tmp0, tmp0, dst, BPS);
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}
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static void TransformAC3(const int16_t* in, uint8_t* dst) {
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const int a = in[0] + 4;
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const int c4 = MULT2(in[4]);
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const int d4 = MULT1(in[4]);
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const int in2 = MULT2(in[1]);
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const int in3 = MULT1(in[1]);
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v4i32 tmp0 = { 0 };
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v4i32 out0 = __msa_fill_w(a + d4);
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v4i32 out1 = __msa_fill_w(a + c4);
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v4i32 out2 = __msa_fill_w(a - c4);
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v4i32 out3 = __msa_fill_w(a - d4);
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v4i32 res0, res1, res2, res3;
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const v4i32 zero = { 0 };
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v16u8 dest0, dest1, dest2, dest3;
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INSERT_W4_SW(in3, in2, -in2, -in3, tmp0);
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ADD4(out0, tmp0, out1, tmp0, out2, tmp0, out3, tmp0,
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out0, out1, out2, out3);
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SRAI_W4_SW(out0, out1, out2, out3, 3);
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LD_UB4(dst, BPS, dest0, dest1, dest2, dest3);
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ILVR_B4_SW(zero, dest0, zero, dest1, zero, dest2, zero, dest3,
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res0, res1, res2, res3);
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ILVR_H4_SW(zero, res0, zero, res1, zero, res2, zero, res3,
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res0, res1, res2, res3);
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ADD4(res0, out0, res1, out1, res2, out2, res3, out3, res0, res1, res2, res3);
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CLIP_SW4_0_255(res0, res1, res2, res3);
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PCKEV_B2_SW(res0, res1, res2, res3, out0, out1);
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res0 = (v4i32)__msa_pckev_b((v16i8)out0, (v16i8)out1);
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ST4x4_UB(res0, res0, 3, 2, 1, 0, dst, BPS);
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}
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//------------------------------------------------------------------------------
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// Entry point
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extern void VP8DspInitMSA(void);
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WEBP_TSAN_IGNORE_FUNCTION void VP8DspInitMSA(void) {
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VP8TransformWHT = TransformWHT;
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VP8Transform = TransformTwo;
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VP8TransformDC = TransformDC;
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VP8TransformAC3 = TransformAC3;
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}
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#else // !WEBP_USE_MSA
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WEBP_DSP_INIT_STUB(VP8DspInitMSA)
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#endif // WEBP_USE_MSA
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555
src/dsp/msa_macro.h
Normal file
555
src/dsp/msa_macro.h
Normal file
@ -0,0 +1,555 @@
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// Copyright 2016 Google Inc. All Rights Reserved.
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//
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// Use of this source code is governed by a BSD-style license
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// that can be found in the COPYING file in the root of the source
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// tree. An additional intellectual property rights grant can be found
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// in the file PATENTS. All contributing project authors may
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// be found in the AUTHORS file in the root of the source tree.
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// -----------------------------------------------------------------------------
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//
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// MSA common macros
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//
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// Author(s): Prashant Patil (prashant.patil@imgtec.com)
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#ifndef WEBP_DSP_MSA_MACRO_H_
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#define WEBP_DSP_MSA_MACRO_H_
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#include <stdint.h>
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#include <msa.h>
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#if defined(__clang__)
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#define CLANG_BUILD
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#endif
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#ifdef CLANG_BUILD
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#define ADDVI_H(a, b) __msa_addvi_h((v8i16)a, b)
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#define SRAI_H(a, b) __msa_srai_h((v8i16)a, b)
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#define SRAI_W(a, b) __msa_srai_w((v4i32)a, b)
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#else
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#define ADDVI_H(a, b) (a + b)
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#define SRAI_H(a, b) (a >> b)
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#define SRAI_W(a, b) (a >> b)
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#endif
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#define LD_B(RTYPE, psrc) *((RTYPE*)(psrc))
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#define LD_UB(...) LD_B(v16u8, __VA_ARGS__)
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#define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
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#define LD_H(RTYPE, psrc) *((RTYPE*)(psrc))
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#define LD_UH(...) LD_H(v8u16, __VA_ARGS__)
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#define LD_SH(...) LD_H(v8i16, __VA_ARGS__)
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#define LD_W(RTYPE, psrc) *((RTYPE*)(psrc))
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#define LD_UW(...) LD_W(v4u32, __VA_ARGS__)
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#define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
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#define ST_B(RTYPE, in, pdst) *((RTYPE*)(pdst)) = in
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#define ST_UB(...) ST_B(v16u8, __VA_ARGS__)
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#define ST_SB(...) ST_B(v16i8, __VA_ARGS__)
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#define ST_H(RTYPE, in, pdst) *((RTYPE*)(pdst)) = in
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#define ST_UH(...) ST_H(v8u16, __VA_ARGS__)
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#define ST_SH(...) ST_H(v8i16, __VA_ARGS__)
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#define ST_W(RTYPE, in, pdst) *((RTYPE*)(pdst)) = in
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#define ST_UW(...) ST_W(v4u32, __VA_ARGS__)
|
||||
#define ST_SW(...) ST_W(v4i32, __VA_ARGS__)
|
||||
|
||||
#define MSA_LOAD_FUNC(TYPE, INSTR, FUNC_NAME) \
|
||||
static inline TYPE FUNC_NAME(const void* const psrc) { \
|
||||
const uint8_t* const psrc_m = (const uint8_t*)psrc; \
|
||||
TYPE val_m; \
|
||||
asm volatile ( \
|
||||
"" #INSTR " %[val_m], %[psrc_m] \n\t" \
|
||||
: [val_m] "=r" (val_m) \
|
||||
: [psrc_m] "m" (*psrc_m)); \
|
||||
return val_m; \
|
||||
}
|
||||
|
||||
#define MSA_LOAD(psrc, FUNC_NAME) FUNC_NAME(psrc)
|
||||
|
||||
#define MSA_STORE_FUNC(TYPE, INSTR, FUNC_NAME) \
|
||||
static inline void FUNC_NAME(TYPE val, void* const pdst) { \
|
||||
uint8_t* const pdst_m = (uint8_t*)pdst; \
|
||||
TYPE val_m = val; \
|
||||
asm volatile ( \
|
||||
" " #INSTR " %[val_m], %[pdst_m] \n\t" \
|
||||
: [pdst_m] "=m" (*pdst_m) \
|
||||
: [val_m] "r" (val_m)); \
|
||||
}
|
||||
|
||||
#define MSA_STORE(val, pdst, FUNC_NAME) FUNC_NAME(val, pdst)
|
||||
|
||||
#if (__mips_isa_rev >= 6)
|
||||
MSA_LOAD_FUNC(uint16_t, lh, msa_lh);
|
||||
#define LH(psrc) MSA_LOAD(psrc, msa_lh)
|
||||
MSA_LOAD_FUNC(uint32_t, lw, msa_lw);
|
||||
#define LW(psrc) MSA_LOAD(psrc, msa_lw)
|
||||
#if (__mips == 64)
|
||||
MSA_LOAD_FUNC(uint64_t, ld, msa_ld);
|
||||
#define LD(psrc) MSA_LOAD(psrc, msa_ld)
|
||||
#else // !(__mips == 64)
|
||||
#define LD(psrc) ((((uint64_t)MSA_LOAD(psrc + 4, msa_lw)) << 32) | \
|
||||
MSA_LOAD(psrc, msa_lw))
|
||||
#endif // (__mips == 64)
|
||||
|
||||
MSA_STORE_FUNC(uint16_t, sh, msa_sh);
|
||||
#define SH(val, pdst) MSA_STORE(val, pdst, msa_sh)
|
||||
MSA_STORE_FUNC(uint32_t, sw, msa_sw);
|
||||
#define SW(val, pdst) MSA_STORE(val, pdst, msa_sw)
|
||||
MSA_STORE_FUNC(uint64_t, sd, msa_sd);
|
||||
#define SD(val, pdst) MSA_STORE(val, pdst, msa_sd)
|
||||
#else // !(__mips_isa_rev >= 6)
|
||||
MSA_LOAD_FUNC(uint16_t, ulh, msa_ulh);
|
||||
#define LH(psrc) MSA_LOAD(psrc, msa_ulh)
|
||||
MSA_LOAD_FUNC(uint32_t, ulw, msa_ulw);
|
||||
#define LW(psrc) MSA_LOAD(psrc, msa_ulw)
|
||||
#if (__mips == 64)
|
||||
MSA_LOAD_FUNC(uint64_t, uld, msa_uld);
|
||||
#define LD(psrc) MSA_LOAD(psrc, msa_uld)
|
||||
#else // !(__mips == 64)
|
||||
#define LD(psrc) ((((uint64_t)MSA_LOAD(psrc + 4, msa_ulw)) << 32) | \
|
||||
MSA_LOAD(psrc, msa_ulw))
|
||||
#endif // (__mips == 64)
|
||||
|
||||
MSA_STORE_FUNC(uint16_t, ush, msa_ush);
|
||||
#define SH(val, pdst) MSA_STORE(val, pdst, msa_ush)
|
||||
MSA_STORE_FUNC(uint32_t, usw, msa_usw);
|
||||
#define SW(val, pdst) MSA_STORE(val, pdst, msa_usw)
|
||||
#define SD(val, pdst) { \
|
||||
uint8_t* const pdst_sd_m = (uint8_t*)(pdst); \
|
||||
const uint32_t val0_m = (uint32_t)(val & 0x00000000FFFFFFFF); \
|
||||
const uint32_t val1_m = (uint32_t)((val >> 32) & 0x00000000FFFFFFFF); \
|
||||
SW(val0_m, pdst_sd_m); \
|
||||
SW(val1_m, pdst_sd_m + 4); \
|
||||
}
|
||||
#endif // (__mips_isa_rev >= 6)
|
||||
|
||||
/* Description : Load 4 words with stride
|
||||
* Arguments : Inputs - psrc, stride
|
||||
* Outputs - out0, out1, out2, out3
|
||||
* Details : Load word in 'out0' from (psrc)
|
||||
* Load word in 'out1' from (psrc + stride)
|
||||
* Load word in 'out2' from (psrc + 2 * stride)
|
||||
* Load word in 'out3' from (psrc + 3 * stride)
|
||||
*/
|
||||
#define LW4(psrc, stride, out0, out1, out2, out3) { \
|
||||
const uint8_t* ptmp = (const uint8_t*)psrc; \
|
||||
out0 = LW(ptmp); \
|
||||
ptmp += stride; \
|
||||
out1 = LW(ptmp); \
|
||||
ptmp += stride; \
|
||||
out2 = LW(ptmp); \
|
||||
ptmp += stride; \
|
||||
out3 = LW(ptmp); \
|
||||
}
|
||||
|
||||
/* Description : Store 4 words with stride
|
||||
* Arguments : Inputs - in0, in1, in2, in3, pdst, stride
|
||||
* Details : Store word from 'in0' to (pdst)
|
||||
* Store word from 'in1' to (pdst + stride)
|
||||
* Store word from 'in2' to (pdst + 2 * stride)
|
||||
* Store word from 'in3' to (pdst + 3 * stride)
|
||||
*/
|
||||
#define SW4(in0, in1, in2, in3, pdst, stride) { \
|
||||
uint8_t* ptmp = (uint8_t*)pdst; \
|
||||
SW(in0, ptmp); \
|
||||
ptmp += stride; \
|
||||
SW(in1, ptmp); \
|
||||
ptmp += stride; \
|
||||
SW(in2, ptmp); \
|
||||
ptmp += stride; \
|
||||
SW(in3, ptmp); \
|
||||
}
|
||||
|
||||
/* Description : Load vectors with 16 byte elements with stride
|
||||
* Arguments : Inputs - psrc, stride
|
||||
* Outputs - out0, out1
|
||||
* Return Type - as per RTYPE
|
||||
* Details : Load 16 byte elements in 'out0' from (psrc)
|
||||
* Load 16 byte elements in 'out1' from (psrc + stride)
|
||||
*/
|
||||
#define LD_B2(RTYPE, psrc, stride, out0, out1) { \
|
||||
out0 = LD_B(RTYPE, psrc); \
|
||||
out1 = LD_B(RTYPE, psrc + stride); \
|
||||
}
|
||||
#define LD_UB2(...) LD_B2(v16u8, __VA_ARGS__)
|
||||
#define LD_SB2(...) LD_B2(v16i8, __VA_ARGS__)
|
||||
|
||||
#define LD_B4(RTYPE, psrc, stride, out0, out1, out2, out3) { \
|
||||
LD_B2(RTYPE, psrc, stride, out0, out1); \
|
||||
LD_B2(RTYPE, psrc + 2 * stride , stride, out2, out3); \
|
||||
}
|
||||
#define LD_UB4(...) LD_B4(v16u8, __VA_ARGS__)
|
||||
#define LD_SB4(...) LD_B4(v16i8, __VA_ARGS__)
|
||||
|
||||
/* Description : Load vectors with 8 halfword elements with stride
|
||||
* Arguments : Inputs - psrc, stride
|
||||
* Outputs - out0, out1
|
||||
* Details : Load 8 halfword elements in 'out0' from (psrc)
|
||||
* Load 8 halfword elements in 'out1' from (psrc + stride)
|
||||
*/
|
||||
#define LD_H2(RTYPE, psrc, stride, out0, out1) { \
|
||||
out0 = LD_H(RTYPE, psrc); \
|
||||
out1 = LD_H(RTYPE, psrc + stride); \
|
||||
}
|
||||
#define LD_UH2(...) LD_H2(v8u16, __VA_ARGS__)
|
||||
#define LD_SH2(...) LD_H2(v8i16, __VA_ARGS__)
|
||||
|
||||
/* Description : Store 4x4 byte block to destination memory from input vector
|
||||
* Arguments : Inputs - in0, in1, pdst, stride
|
||||
* Details : 'Idx0' word element from input vector 'in0' is copied to the
|
||||
* GP register and stored to (pdst)
|
||||
* 'Idx1' word element from input vector 'in0' is copied to the
|
||||
* GP register and stored to (pdst + stride)
|
||||
* 'Idx2' word element from input vector 'in0' is copied to the
|
||||
* GP register and stored to (pdst + 2 * stride)
|
||||
* 'Idx3' word element from input vector 'in0' is copied to the
|
||||
* GP register and stored to (pdst + 3 * stride)
|
||||
*/
|
||||
#define ST4x4_UB(in0, in1, idx0, idx1, idx2, idx3, pdst, stride) { \
|
||||
uint8_t* const pblk_4x4_m = (uint8_t*)pdst; \
|
||||
const uint32_t out0_m = __msa_copy_s_w((v4i32)in0, idx0); \
|
||||
const uint32_t out1_m = __msa_copy_s_w((v4i32)in0, idx1); \
|
||||
const uint32_t out2_m = __msa_copy_s_w((v4i32)in1, idx2); \
|
||||
const uint32_t out3_m = __msa_copy_s_w((v4i32)in1, idx3); \
|
||||
SW4(out0_m, out1_m, out2_m, out3_m, pblk_4x4_m, stride); \
|
||||
}
|
||||
|
||||
/* Description : Immediate number of elements to slide
|
||||
* Arguments : Inputs - in0, in1, slide_val
|
||||
* Outputs - out
|
||||
* Return Type - as per RTYPE
|
||||
* Details : Byte elements from 'in1' vector are slid into 'in0' by
|
||||
* value specified in the 'slide_val'
|
||||
*/
|
||||
#define SLDI_B(RTYPE, in0, in1, slide_val) \
|
||||
(RTYPE)__msa_sldi_b((v16i8)in0, (v16i8)in1, slide_val) \
|
||||
|
||||
#define SLDI_UB(...) SLDI_B(v16u8, __VA_ARGS__)
|
||||
#define SLDI_SB(...) SLDI_B(v16i8, __VA_ARGS__)
|
||||
#define SLDI_SH(...) SLDI_B(v8i16, __VA_ARGS__)
|
||||
|
||||
/* Description : Shuffle halfword vector elements as per mask vector
|
||||
* Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
|
||||
* Outputs - out0, out1
|
||||
* Return Type - as per RTYPE
|
||||
* Details : halfword elements from 'in0' & 'in1' are copied selectively to
|
||||
* 'out0' as per control vector 'mask0'
|
||||
*/
|
||||
#define VSHF_H2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) { \
|
||||
out0 = (RTYPE)__msa_vshf_h((v8i16)mask0, (v8i16)in1, (v8i16)in0); \
|
||||
out1 = (RTYPE)__msa_vshf_h((v8i16)mask1, (v8i16)in3, (v8i16)in2); \
|
||||
}
|
||||
#define VSHF_H2_UH(...) VSHF_H2(v8u16, __VA_ARGS__)
|
||||
#define VSHF_H2_SH(...) VSHF_H2(v8i16, __VA_ARGS__)
|
||||
|
||||
/* Description : Clips all signed halfword elements of input vector
|
||||
* between 0 & 255
|
||||
* Arguments : Input/output - val
|
||||
* Return Type - signed halfword
|
||||
*/
|
||||
#define CLIP_SH_0_255(val) { \
|
||||
const v8i16 max_m = __msa_ldi_h(255); \
|
||||
val = __msa_maxi_s_h((v8i16)val, 0); \
|
||||
val = __msa_min_s_h(max_m, (v8i16)val); \
|
||||
}
|
||||
#define CLIP_SH2_0_255(in0, in1) { \
|
||||
CLIP_SH_0_255(in0); \
|
||||
CLIP_SH_0_255(in1); \
|
||||
}
|
||||
|
||||
/* Description : Clips all signed word elements of input vector
|
||||
* between 0 & 255
|
||||
* Arguments : Input/output - val
|
||||
* Return Type - signed word
|
||||
*/
|
||||
#define CLIP_SW_0_255(val) { \
|
||||
const v4i32 max_m = __msa_ldi_w(255); \
|
||||
val = __msa_maxi_s_w((v4i32)val, 0); \
|
||||
val = __msa_min_s_w(max_m, (v4i32)val); \
|
||||
}
|
||||
#define CLIP_SW4_0_255(in0, in1, in2, in3) { \
|
||||
CLIP_SW_0_255(in0); \
|
||||
CLIP_SW_0_255(in1); \
|
||||
CLIP_SW_0_255(in2); \
|
||||
CLIP_SW_0_255(in3); \
|
||||
}
|
||||
|
||||
/* Description : Set element n input vector to GPR value
|
||||
* Arguments : Inputs - in0, in1, in2, in3
|
||||
* Output - out
|
||||
* Return Type - as per RTYPE
|
||||
* Details : Set element 0 in vector 'out' to value specified in 'in0'
|
||||
*/
|
||||
#define INSERT_W2(RTYPE, in0, in1, out) { \
|
||||
out = (RTYPE)__msa_insert_w((v4i32)out, 0, in0); \
|
||||
out = (RTYPE)__msa_insert_w((v4i32)out, 1, in1); \
|
||||
}
|
||||
#define INSERT_W2_UB(...) INSERT_W2(v16u8, __VA_ARGS__)
|
||||
#define INSERT_W2_SB(...) INSERT_W2(v16i8, __VA_ARGS__)
|
||||
|
||||
#define INSERT_W4(RTYPE, in0, in1, in2, in3, out) { \
|
||||
out = (RTYPE)__msa_insert_w((v4i32)out, 0, in0); \
|
||||
out = (RTYPE)__msa_insert_w((v4i32)out, 1, in1); \
|
||||
out = (RTYPE)__msa_insert_w((v4i32)out, 2, in2); \
|
||||
out = (RTYPE)__msa_insert_w((v4i32)out, 3, in3); \
|
||||
}
|
||||
#define INSERT_W4_UB(...) INSERT_W4(v16u8, __VA_ARGS__)
|
||||
#define INSERT_W4_SB(...) INSERT_W4(v16i8, __VA_ARGS__)
|
||||
#define INSERT_W4_SW(...) INSERT_W4(v4i32, __VA_ARGS__)
|
||||
|
||||
/* Description : Interleave right half of byte elements from vectors
|
||||
* Arguments : Inputs - in0, in1, in2, in3
|
||||
* Outputs - out0, out1
|
||||
* Return Type - as per RTYPE
|
||||
* Details : Right half of byte elements of 'in0' and 'in1' are interleaved
|
||||
* and written to out0.
|
||||
*/
|
||||
#define ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1) { \
|
||||
out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \
|
||||
out1 = (RTYPE)__msa_ilvr_b((v16i8)in2, (v16i8)in3); \
|
||||
}
|
||||
#define ILVR_B2_UB(...) ILVR_B2(v16u8, __VA_ARGS__)
|
||||
#define ILVR_B2_SB(...) ILVR_B2(v16i8, __VA_ARGS__)
|
||||
#define ILVR_B2_UH(...) ILVR_B2(v8u16, __VA_ARGS__)
|
||||
#define ILVR_B2_SH(...) ILVR_B2(v8i16, __VA_ARGS__)
|
||||
#define ILVR_B2_SW(...) ILVR_B2(v4i32, __VA_ARGS__)
|
||||
|
||||
#define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
|
||||
out0, out1, out2, out3) { \
|
||||
ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1); \
|
||||
ILVR_B2(RTYPE, in4, in5, in6, in7, out2, out3); \
|
||||
}
|
||||
#define ILVR_B4_UB(...) ILVR_B4(v16u8, __VA_ARGS__)
|
||||
#define ILVR_B4_SB(...) ILVR_B4(v16i8, __VA_ARGS__)
|
||||
#define ILVR_B4_UH(...) ILVR_B4(v8u16, __VA_ARGS__)
|
||||
#define ILVR_B4_SH(...) ILVR_B4(v8i16, __VA_ARGS__)
|
||||
#define ILVR_B4_SW(...) ILVR_B4(v4i32, __VA_ARGS__)
|
||||
|
||||
/* Description : Interleave right half of halfword elements from vectors
|
||||
* Arguments : Inputs - in0, in1, in2, in3
|
||||
* Outputs - out0, out1
|
||||
* Return Type - as per RTYPE
|
||||
* Details : Right half of halfword elements of 'in0' and 'in1' are
|
||||
* interleaved and written to 'out0'.
|
||||
*/
|
||||
#define ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1) { \
|
||||
out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \
|
||||
out1 = (RTYPE)__msa_ilvr_h((v8i16)in2, (v8i16)in3); \
|
||||
}
|
||||
#define ILVR_H2_UB(...) ILVR_H2(v16u8, __VA_ARGS__)
|
||||
#define ILVR_H2_SH(...) ILVR_H2(v8i16, __VA_ARGS__)
|
||||
#define ILVR_H2_SW(...) ILVR_H2(v4i32, __VA_ARGS__)
|
||||
|
||||
#define ILVR_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
|
||||
out0, out1, out2, out3) { \
|
||||
ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1); \
|
||||
ILVR_H2(RTYPE, in4, in5, in6, in7, out2, out3); \
|
||||
}
|
||||
#define ILVR_H4_UB(...) ILVR_H4(v16u8, __VA_ARGS__)
|
||||
#define ILVR_H4_SH(...) ILVR_H4(v8i16, __VA_ARGS__)
|
||||
#define ILVR_H4_SW(...) ILVR_H4(v4i32, __VA_ARGS__)
|
||||
|
||||
/* Description : Interleave right half of double word elements from vectors
|
||||
* Arguments : Inputs - in0, in1, in2, in3
|
||||
* Outputs - out0, out1
|
||||
* Return Type - as per RTYPE
|
||||
* Details : Right half of double word elements of 'in0' and 'in1' are
|
||||
* interleaved and written to 'out0'.
|
||||
*/
|
||||
#define ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1) { \
|
||||
out0 = (RTYPE)__msa_ilvr_d((v2i64)in0, (v2i64)in1); \
|
||||
out1 = (RTYPE)__msa_ilvr_d((v2i64)in2, (v2i64)in3); \
|
||||
}
|
||||
#define ILVR_D2_UB(...) ILVR_D2(v16u8, __VA_ARGS__)
|
||||
#define ILVR_D2_SB(...) ILVR_D2(v16i8, __VA_ARGS__)
|
||||
#define ILVR_D2_SH(...) ILVR_D2(v8i16, __VA_ARGS__)
|
||||
|
||||
#define ILVRL_H2(RTYPE, in0, in1, out0, out1) { \
|
||||
out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \
|
||||
out1 = (RTYPE)__msa_ilvl_h((v8i16)in0, (v8i16)in1); \
|
||||
}
|
||||
#define ILVRL_H2_UB(...) ILVRL_H2(v16u8, __VA_ARGS__)
|
||||
#define ILVRL_H2_SB(...) ILVRL_H2(v16i8, __VA_ARGS__)
|
||||
#define ILVRL_H2_SH(...) ILVRL_H2(v8i16, __VA_ARGS__)
|
||||
#define ILVRL_H2_SW(...) ILVRL_H2(v4i32, __VA_ARGS__)
|
||||
#define ILVRL_H2_UW(...) ILVRL_H2(v4u32, __VA_ARGS__)
|
||||
|
||||
#define ILVRL_W2(RTYPE, in0, in1, out0, out1) { \
|
||||
out0 = (RTYPE)__msa_ilvr_w((v4i32)in0, (v4i32)in1); \
|
||||
out1 = (RTYPE)__msa_ilvl_w((v4i32)in0, (v4i32)in1); \
|
||||
}
|
||||
#define ILVRL_W2_UB(...) ILVRL_W2(v16u8, __VA_ARGS__)
|
||||
#define ILVRL_W2_SH(...) ILVRL_W2(v8i16, __VA_ARGS__)
|
||||
#define ILVRL_W2_SW(...) ILVRL_W2(v4i32, __VA_ARGS__)
|
||||
|
||||
/* Description : Pack even byte elements of vector pairs
|
||||
* Arguments : Inputs - in0, in1, in2, in3
|
||||
* Outputs - out0, out1
|
||||
* Return Type - as per RTYPE
|
||||
* Details : Even byte elements of 'in0' are copied to the left half of
|
||||
* 'out0' & even byte elements of 'in1' are copied to the right
|
||||
* half of 'out0'.
|
||||
*/
|
||||
#define PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) { \
|
||||
out0 = (RTYPE)__msa_pckev_b((v16i8)in0, (v16i8)in1); \
|
||||
out1 = (RTYPE)__msa_pckev_b((v16i8)in2, (v16i8)in3); \
|
||||
}
|
||||
#define PCKEV_B2_SB(...) PCKEV_B2(v16i8, __VA_ARGS__)
|
||||
#define PCKEV_B2_UB(...) PCKEV_B2(v16u8, __VA_ARGS__)
|
||||
#define PCKEV_B2_SH(...) PCKEV_B2(v8i16, __VA_ARGS__)
|
||||
#define PCKEV_B2_SW(...) PCKEV_B2(v4i32, __VA_ARGS__)
|
||||
|
||||
/* Description : Arithmetic immediate shift right all elements of word vector
|
||||
* Arguments : Inputs - in0, in1, shift
|
||||
* Outputs - in place operation
|
||||
* Return Type - as per input vector RTYPE
|
||||
* Details : Each element of vector 'in0' is right shifted by 'shift' and
|
||||
* the result is written in-place. 'shift' is a GP variable.
|
||||
*/
|
||||
#define SRAI_W2(RTYPE, in0, in1, shift_val) { \
|
||||
in0 = (RTYPE)SRAI_W(in0, shift_val); \
|
||||
in1 = (RTYPE)SRAI_W(in1, shift_val); \
|
||||
}
|
||||
#define SRAI_W2_SW(...) SRAI_W2(v4i32, __VA_ARGS__)
|
||||
#define SRAI_W2_UW(...) SRAI_W2(v4u32, __VA_ARGS__)
|
||||
|
||||
#define SRAI_W4(RTYPE, in0, in1, in2, in3, shift_val) { \
|
||||
SRAI_W2(RTYPE, in0, in1, shift_val); \
|
||||
SRAI_W2(RTYPE, in2, in3, shift_val); \
|
||||
}
|
||||
#define SRAI_W4_SW(...) SRAI_W4(v4i32, __VA_ARGS__)
|
||||
#define SRAI_W4_UW(...) SRAI_W4(v4u32, __VA_ARGS__)
|
||||
|
||||
/* Description : Arithmetic shift right all elements of half-word vector
|
||||
* Arguments : Inputs - in0, in1, shift
|
||||
* Outputs - in place operation
|
||||
* Return Type - as per input vector RTYPE
|
||||
* Details : Each element of vector 'in0' is right shifted by 'shift' and
|
||||
* the result is written in-place. 'shift' is a GP variable.
|
||||
*/
|
||||
#define SRAI_H2(RTYPE, in0, in1, shift_val) { \
|
||||
in0 = (RTYPE)SRAI_H(in0, shift_val); \
|
||||
in1 = (RTYPE)SRAI_H(in1, shift_val); \
|
||||
}
|
||||
#define SRAI_H2_SH(...) SRAI_H2(v8i16, __VA_ARGS__)
|
||||
#define SRAI_H2_UH(...) SRAI_H2(v8u16, __VA_ARGS__)
|
||||
|
||||
/* Description : Arithmetic rounded shift right all elements of word vector
|
||||
* Arguments : Inputs - in0, in1, shift
|
||||
* Outputs - in place operation
|
||||
* Return Type - as per input vector RTYPE
|
||||
* Details : Each element of vector 'in0' is right shifted by 'shift' and
|
||||
* the result is written in-place. 'shift' is a GP variable.
|
||||
*/
|
||||
#define SRARI_W2(RTYPE, in0, in1, shift) { \
|
||||
in0 = (RTYPE)__msa_srari_w((v4i32)in0, shift); \
|
||||
in1 = (RTYPE)__msa_srari_w((v4i32)in1, shift); \
|
||||
}
|
||||
#define SRARI_W2_SW(...) SRARI_W2(v4i32, __VA_ARGS__)
|
||||
|
||||
#define SRARI_W4(RTYPE, in0, in1, in2, in3, shift) { \
|
||||
SRARI_W2(RTYPE, in0, in1, shift); \
|
||||
SRARI_W2(RTYPE, in2, in3, shift); \
|
||||
}
|
||||
#define SRARI_W4_SH(...) SRARI_W4(v8i16, __VA_ARGS__)
|
||||
#define SRARI_W4_UW(...) SRARI_W4(v4u32, __VA_ARGS__)
|
||||
#define SRARI_W4_SW(...) SRARI_W4(v4i32, __VA_ARGS__)
|
||||
|
||||
/* Description : Addition of 2 pairs of half-word vectors
|
||||
* Arguments : Inputs - in0, in1, in2, in3
|
||||
* Outputs - out0, out1
|
||||
* Details : Each element in 'in0' is added to 'in1' and result is written
|
||||
* to 'out0'.
|
||||
*/
|
||||
#define ADDVI_H2(RTYPE, in0, in1, in2, in3, out0, out1) { \
|
||||
out0 = (RTYPE)ADDVI_H(in0, in1); \
|
||||
out1 = (RTYPE)ADDVI_H(in2, in3); \
|
||||
}
|
||||
#define ADDVI_H2_SH(...) ADDVI_H2(v8i16, __VA_ARGS__)
|
||||
#define ADDVI_H2_UH(...) ADDVI_H2(v8u16, __VA_ARGS__)
|
||||
|
||||
/* Description : Addition of 2 pairs of vectors
|
||||
* Arguments : Inputs - in0, in1, in2, in3
|
||||
* Outputs - out0, out1
|
||||
* Details : Each element in 'in0' is added to 'in1' and result is written
|
||||
* to 'out0'.
|
||||
*/
|
||||
#define ADD2(in0, in1, in2, in3, out0, out1) { \
|
||||
out0 = in0 + in1; \
|
||||
out1 = in2 + in3; \
|
||||
}
|
||||
#define ADD4(in0, in1, in2, in3, in4, in5, in6, in7, \
|
||||
out0, out1, out2, out3) { \
|
||||
ADD2(in0, in1, in2, in3, out0, out1); \
|
||||
ADD2(in4, in5, in6, in7, out2, out3); \
|
||||
}
|
||||
|
||||
/* Description : Sign extend halfword elements from input vector and return
|
||||
* the result in pair of vectors
|
||||
* Arguments : Input - in (halfword vector)
|
||||
* Outputs - out0, out1 (sign extended word vectors)
|
||||
* Return Type - signed word
|
||||
* Details : Sign bit of halfword elements from input vector 'in' is
|
||||
* extracted and interleaved right with same vector 'in0' to
|
||||
* generate 4 signed word elements in 'out0'
|
||||
* Then interleaved left with same vector 'in0' to
|
||||
* generate 4 signed word elements in 'out1'
|
||||
*/
|
||||
#define UNPCK_SH_SW(in, out0, out1) { \
|
||||
const v8i16 tmp_m = __msa_clti_s_h((v8i16)in, 0); \
|
||||
ILVRL_H2_SW(tmp_m, in, out0, out1); \
|
||||
}
|
||||
|
||||
/* Description : Butterfly of 4 input vectors
|
||||
* Arguments : Inputs - in0, in1, in2, in3
|
||||
* Outputs - out0, out1, out2, out3
|
||||
* Details : Butterfly operation
|
||||
*/
|
||||
#define BUTTERFLY_4(in0, in1, in2, in3, out0, out1, out2, out3) { \
|
||||
out0 = in0 + in3; \
|
||||
out1 = in1 + in2; \
|
||||
out2 = in1 - in2; \
|
||||
out3 = in0 - in3; \
|
||||
}
|
||||
|
||||
/* Description : Transpose 4x4 block with word elements in vectors
|
||||
* Arguments : Inputs - in0, in1, in2, in3
|
||||
* Outputs - out0, out1, out2, out3
|
||||
* Return Type - as per RTYPE
|
||||
*/
|
||||
#define TRANSPOSE4x4_W(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3) { \
|
||||
v4i32 s0_m, s1_m, s2_m, s3_m; \
|
||||
ILVRL_W2_SW(in1, in0, s0_m, s1_m); \
|
||||
ILVRL_W2_SW(in3, in2, s2_m, s3_m); \
|
||||
out0 = (RTYPE)__msa_ilvr_d((v2i64)s2_m, (v2i64)s0_m); \
|
||||
out1 = (RTYPE)__msa_ilvl_d((v2i64)s2_m, (v2i64)s0_m); \
|
||||
out2 = (RTYPE)__msa_ilvr_d((v2i64)s3_m, (v2i64)s1_m); \
|
||||
out3 = (RTYPE)__msa_ilvl_d((v2i64)s3_m, (v2i64)s1_m); \
|
||||
}
|
||||
#define TRANSPOSE4x4_SW_SW(...) TRANSPOSE4x4_W(v4i32, __VA_ARGS__)
|
||||
|
||||
/* Description : Add block 4x4
|
||||
* Arguments : Inputs - in0, in1, in2, in3, pdst, stride
|
||||
* Details : Least significant 4 bytes from each input vector are added to
|
||||
* the destination bytes, clipped between 0-255 and stored.
|
||||
*/
|
||||
#define ADDBLK_ST4x4_UB(in0, in1, in2, in3, pdst, stride) { \
|
||||
uint32_t src0_m, src1_m, src2_m, src3_m; \
|
||||
v8i16 inp0_m, inp1_m, res0_m, res1_m; \
|
||||
v16i8 dst0_m = { 0 }; \
|
||||
v16i8 dst1_m = { 0 }; \
|
||||
const v16i8 zero_m = { 0 }; \
|
||||
ILVR_D2_SH(in1, in0, in3, in2, inp0_m, inp1_m); \
|
||||
LW4(pdst, stride, src0_m, src1_m, src2_m, src3_m); \
|
||||
INSERT_W2_SB(src0_m, src1_m, dst0_m); \
|
||||
INSERT_W2_SB(src2_m, src3_m, dst1_m); \
|
||||
ILVR_B2_SH(zero_m, dst0_m, zero_m, dst1_m, res0_m, res1_m); \
|
||||
ADD2(res0_m, inp0_m, res1_m, inp1_m, res0_m, res1_m); \
|
||||
CLIP_SH2_0_255(res0_m, res1_m); \
|
||||
PCKEV_B2_SB(res0_m, res0_m, res1_m, res1_m, dst0_m, dst1_m); \
|
||||
ST4x4_UB(dst0_m, dst1_m, 0, 1, 0, 1, pdst, stride); \
|
||||
}
|
||||
|
||||
#endif /* WEBP_DSP_MSA_MACRO_H_ */
|
||||
Loading…
Reference in New Issue
Block a user