e3f850ee05
The current code stores pointers to coefficient tables and loads them to access the tables contents. As these pointers are stored in the code sections, it means we end up with text relocations. eu-findtextrel will thus complain about code not compiled with -fpic/-fPIC. Since the pointers are stored in the code sections, we can actually cheat and let the assembler generate relative addressing when accessing the coefficient tables, and just load their location with adr. Change-Id: Ib74ae2d3f2bab80b29991355f2dbe6955f38f6ae
198 lines
5.9 KiB
NASM
198 lines
5.9 KiB
NASM
;
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; Copyright (c) 2010 The Webm project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |idct_dequant_full_2x_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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;void idct_dequant_full_2x_neon(short *q, short *dq, unsigned char *pre,
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; unsigned char *dst, int pitch, int stride);
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; r0 *q,
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; r1 *dq,
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; r2 *pre
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; r3 *dst
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; sp pitch
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; sp+4 stride
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|idct_dequant_full_2x_neon| PROC
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vld1.16 {q0, q1}, [r1] ; dq (same l/r)
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vld1.16 {q2, q3}, [r0] ; l q
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ldr r1, [sp] ; pitch
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add r0, r0, #32
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vld1.16 {q4, q5}, [r0] ; r q
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add r12, r2, #4
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; interleave the predictors
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vld1.32 {d28[0]}, [r2], r1 ; l pre
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vld1.32 {d28[1]}, [r12], r1 ; r pre
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vld1.32 {d29[0]}, [r2], r1
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vld1.32 {d29[1]}, [r12], r1
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vld1.32 {d30[0]}, [r2], r1
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vld1.32 {d30[1]}, [r12], r1
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vld1.32 {d31[0]}, [r2]
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vld1.32 {d31[1]}, [r12]
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adr r2, cospi8sqrt2minus1 ; pointer to the first constant
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; dequant: q[i] = q[i] * dq[i]
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vmul.i16 q2, q2, q0
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vmul.i16 q3, q3, q1
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vmul.i16 q4, q4, q0
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vmul.i16 q5, q5, q1
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vld1.16 {d0}, [r2]
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; q2: l0r0 q3: l8r8
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; q4: l4r4 q5: l12r12
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vswp d5, d8
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vswp d7, d10
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; _CONSTANTS_ * 4,12 >> 16
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; q6: 4 * sinpi : c1/temp1
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; q7: 12 * sinpi : d1/temp2
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; q8: 4 * cospi
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; q9: 12 * cospi
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vqdmulh.s16 q6, q4, d0[2] ; sinpi8sqrt2
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vqdmulh.s16 q7, q5, d0[2]
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vqdmulh.s16 q8, q4, d0[0] ; cospi8sqrt2minus1
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vqdmulh.s16 q9, q5, d0[0]
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vqadd.s16 q10, q2, q3 ; a1 = 0 + 8
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vqsub.s16 q11, q2, q3 ; b1 = 0 - 8
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; vqdmulh only accepts signed values. this was a problem because
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; our constant had the high bit set, and was treated as a negative value.
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; vqdmulh also doubles the value before it shifts by 16. we need to
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; compensate for this. in the case of sinpi8sqrt2, the lowest bit is 0,
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; so we can shift the constant without losing precision. this avoids
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; shift again afterward, but also avoids the sign issue. win win!
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; for cospi8sqrt2minus1 the lowest bit is 1, so we lose precision if we
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; pre-shift it
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vshr.s16 q8, q8, #1
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vshr.s16 q9, q9, #1
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; q4: 4 + 4 * cospi : d1/temp1
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; q5: 12 + 12 * cospi : c1/temp2
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vqadd.s16 q4, q4, q8
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vqadd.s16 q5, q5, q9
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; c1 = temp1 - temp2
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; d1 = temp1 + temp2
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vqsub.s16 q2, q6, q5
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vqadd.s16 q3, q4, q7
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; [0]: a1+d1
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; [1]: b1+c1
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; [2]: b1-c1
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; [3]: a1-d1
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vqadd.s16 q4, q10, q3
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vqadd.s16 q5, q11, q2
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vqsub.s16 q6, q11, q2
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vqsub.s16 q7, q10, q3
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; rotate
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vtrn.32 q4, q6
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vtrn.32 q5, q7
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vtrn.16 q4, q5
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vtrn.16 q6, q7
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; idct loop 2
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; q4: l 0, 4, 8,12 r 0, 4, 8,12
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; q5: l 1, 5, 9,13 r 1, 5, 9,13
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; q6: l 2, 6,10,14 r 2, 6,10,14
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; q7: l 3, 7,11,15 r 3, 7,11,15
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; q8: 1 * sinpi : c1/temp1
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; q9: 3 * sinpi : d1/temp2
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; q10: 1 * cospi
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; q11: 3 * cospi
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vqdmulh.s16 q8, q5, d0[2] ; sinpi8sqrt2
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vqdmulh.s16 q9, q7, d0[2]
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vqdmulh.s16 q10, q5, d0[0] ; cospi8sqrt2minus1
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vqdmulh.s16 q11, q7, d0[0]
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vqadd.s16 q2, q4, q6 ; a1 = 0 + 2
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vqsub.s16 q3, q4, q6 ; b1 = 0 - 2
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; see note on shifting above
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vshr.s16 q10, q10, #1
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vshr.s16 q11, q11, #1
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; q10: 1 + 1 * cospi : d1/temp1
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; q11: 3 + 3 * cospi : c1/temp2
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vqadd.s16 q10, q5, q10
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vqadd.s16 q11, q7, q11
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; q8: c1 = temp1 - temp2
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; q9: d1 = temp1 + temp2
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vqsub.s16 q8, q8, q11
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vqadd.s16 q9, q10, q9
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; a1+d1
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; b1+c1
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; b1-c1
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; a1-d1
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vqadd.s16 q4, q2, q9
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vqadd.s16 q5, q3, q8
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vqsub.s16 q6, q3, q8
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vqsub.s16 q7, q2, q9
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; +4 >> 3 (rounding)
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vrshr.s16 q4, q4, #3 ; lo
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vrshr.s16 q5, q5, #3
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vrshr.s16 q6, q6, #3 ; hi
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vrshr.s16 q7, q7, #3
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vtrn.32 q4, q6
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vtrn.32 q5, q7
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vtrn.16 q4, q5
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vtrn.16 q6, q7
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; adding pre
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; input is still packed. pre was read interleaved
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vaddw.u8 q4, q4, d28
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vaddw.u8 q5, q5, d29
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vaddw.u8 q6, q6, d30
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vaddw.u8 q7, q7, d31
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vmov.i16 q14, #0
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vmov q15, q14
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vst1.16 {q14, q15}, [r0] ; write over high input
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sub r0, r0, #32
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vst1.16 {q14, q15}, [r0] ; write over low input
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;saturate and narrow
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vqmovun.s16 d0, q4 ; lo
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vqmovun.s16 d1, q5
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vqmovun.s16 d2, q6 ; hi
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vqmovun.s16 d3, q7
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ldr r1, [sp, #4] ; stride
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add r2, r3, #4 ; hi
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vst1.32 {d0[0]}, [r3], r1 ; lo
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vst1.32 {d0[1]}, [r2], r1 ; hi
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vst1.32 {d1[0]}, [r3], r1
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vst1.32 {d1[1]}, [r2], r1
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vst1.32 {d2[0]}, [r3], r1
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vst1.32 {d2[1]}, [r2], r1
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vst1.32 {d3[0]}, [r3]
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vst1.32 {d3[1]}, [r2]
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bx lr
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ENDP ; |idct_dequant_full_2x_neon|
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; Constant Pool
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cospi8sqrt2minus1 DCD 0x4e7b
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; because the lowest bit in 0x8a8c is 0, we can pre-shift this
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sinpi8sqrt2 DCD 0x4546
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END
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