238 lines
6.8 KiB
NASM
238 lines
6.8 KiB
NASM
;
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; Copyright (c) 2013 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vp9_iht4x4_16_add_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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; Parallel 1D IDCT on all the columns of a 4x4 16bits data matrix which are
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; loaded in d16-d19. d0 must contain cospi_8_64. d1 must contain
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; cospi_16_64. d2 must contain cospi_24_64. The output will be stored back
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; into d16-d19 registers. This macro will touch q10- q15 registers and use
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; them as buffer during calculation.
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MACRO
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IDCT4x4_1D
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; stage 1
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vadd.s16 d23, d16, d18 ; (input[0] + input[2])
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vsub.s16 d24, d16, d18 ; (input[0] - input[2])
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vmull.s16 q15, d17, d2 ; input[1] * cospi_24_64
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vmull.s16 q10, d17, d0 ; input[1] * cospi_8_64
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vmull.s16 q13, d23, d1 ; (input[0] + input[2]) * cospi_16_64
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vmull.s16 q14, d24, d1 ; (input[0] - input[2]) * cospi_16_64
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vmlsl.s16 q15, d19, d0 ; input[1] * cospi_24_64 - input[3] * cospi_8_64
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vmlal.s16 q10, d19, d2 ; input[1] * cospi_8_64 + input[3] * cospi_24_64
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; dct_const_round_shift
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vqrshrn.s32 d26, q13, #14
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vqrshrn.s32 d27, q14, #14
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vqrshrn.s32 d29, q15, #14
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vqrshrn.s32 d28, q10, #14
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; stage 2
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; output[0] = step[0] + step[3];
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; output[1] = step[1] + step[2];
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; output[3] = step[0] - step[3];
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; output[2] = step[1] - step[2];
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vadd.s16 q8, q13, q14
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vsub.s16 q9, q13, q14
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vswp d18, d19
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MEND
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; Parallel 1D IADST on all the columns of a 4x4 16bits data matrix which
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; loaded in d16-d19. d3 must contain sinpi_1_9. d4 must contain sinpi_2_9.
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; d5 must contain sinpi_4_9. d6 must contain sinpi_3_9. The output will be
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; stored back into d16-d19 registers. This macro will touch q11,q12,q13,
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; q14,q15 registers and use them as buffer during calculation.
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MACRO
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IADST4x4_1D
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vmull.s16 q10, d3, d16 ; s0 = sinpi_1_9 * x0
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vmull.s16 q11, d4, d16 ; s1 = sinpi_2_9 * x0
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vmull.s16 q12, d6, d17 ; s2 = sinpi_3_9 * x1
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vmull.s16 q13, d5, d18 ; s3 = sinpi_4_9 * x2
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vmull.s16 q14, d3, d18 ; s4 = sinpi_1_9 * x2
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vmovl.s16 q15, d16 ; expand x0 from 16 bit to 32 bit
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vaddw.s16 q15, q15, d19 ; x0 + x3
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vmull.s16 q8, d4, d19 ; s5 = sinpi_2_9 * x3
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vsubw.s16 q15, q15, d18 ; s7 = x0 + x3 - x2
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vmull.s16 q9, d5, d19 ; s6 = sinpi_4_9 * x3
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vadd.s32 q10, q10, q13 ; x0 = s0 + s3 + s5
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vadd.s32 q10, q10, q8
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vsub.s32 q11, q11, q14 ; x1 = s1 - s4 - s6
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vdup.32 q8, r0 ; duplicate sinpi_3_9
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vsub.s32 q11, q11, q9
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vmul.s32 q15, q15, q8 ; x2 = sinpi_3_9 * s7
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vadd.s32 q13, q10, q12 ; s0 = x0 + x3
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vadd.s32 q10, q10, q11 ; x0 + x1
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vadd.s32 q14, q11, q12 ; s1 = x1 + x3
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vsub.s32 q10, q10, q12 ; s3 = x0 + x1 - x3
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; dct_const_round_shift
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vqrshrn.s32 d16, q13, #14
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vqrshrn.s32 d17, q14, #14
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vqrshrn.s32 d18, q15, #14
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vqrshrn.s32 d19, q10, #14
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MEND
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; Generate cosine constants in d6 - d8 for the IDCT
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MACRO
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GENERATE_COSINE_CONSTANTS
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; cospi_8_64 = 15137 = 0x3b21
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mov r0, #0x3b00
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add r0, #0x21
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; cospi_16_64 = 11585 = 0x2d41
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mov r3, #0x2d00
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add r3, #0x41
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; cospi_24_64 = 6270 = 0x187e
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mov r12, #0x1800
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add r12, #0x7e
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; generate constant vectors
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vdup.16 d0, r0 ; duplicate cospi_8_64
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vdup.16 d1, r3 ; duplicate cospi_16_64
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vdup.16 d2, r12 ; duplicate cospi_24_64
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MEND
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; Generate sine constants in d1 - d4 for the IADST.
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MACRO
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GENERATE_SINE_CONSTANTS
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; sinpi_1_9 = 5283 = 0x14A3
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mov r0, #0x1400
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add r0, #0xa3
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; sinpi_2_9 = 9929 = 0x26C9
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mov r3, #0x2600
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add r3, #0xc9
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; sinpi_4_9 = 15212 = 0x3B6C
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mov r12, #0x3b00
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add r12, #0x6c
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; generate constant vectors
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vdup.16 d3, r0 ; duplicate sinpi_1_9
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; sinpi_3_9 = 13377 = 0x3441
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mov r0, #0x3400
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add r0, #0x41
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vdup.16 d4, r3 ; duplicate sinpi_2_9
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vdup.16 d5, r12 ; duplicate sinpi_4_9
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vdup.16 q3, r0 ; duplicate sinpi_3_9
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MEND
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; Transpose a 4x4 16bits data matrix. Datas are loaded in d16-d19.
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MACRO
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TRANSPOSE4X4
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vtrn.16 d16, d17
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vtrn.16 d18, d19
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vtrn.32 q8, q9
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MEND
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AREA Block, CODE, READONLY ; name this block of code
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;void vp9_iht4x4_16_add_neon(int16_t *input, uint8_t *dest,
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; int dest_stride, int tx_type)
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;
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; r0 int16_t input
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; r1 uint8_t *dest
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; r2 int dest_stride
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; r3 int tx_type)
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; This function will only handle tx_type of 1,2,3.
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|vp9_iht4x4_16_add_neon| PROC
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; load the inputs into d16-d19
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vld1.s16 {q8,q9}, [r0]!
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; transpose the input data
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TRANSPOSE4X4
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; decide the type of transform
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cmp r3, #2
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beq idct_iadst
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cmp r3, #3
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beq iadst_iadst
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iadst_idct
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; generate constants
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GENERATE_COSINE_CONSTANTS
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GENERATE_SINE_CONSTANTS
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; first transform rows
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IDCT4x4_1D
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; transpose the matrix
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TRANSPOSE4X4
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; then transform columns
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IADST4x4_1D
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b end_vp9_iht4x4_16_add_neon
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idct_iadst
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; generate constants
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GENERATE_COSINE_CONSTANTS
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GENERATE_SINE_CONSTANTS
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; first transform rows
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IADST4x4_1D
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; transpose the matrix
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TRANSPOSE4X4
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; then transform columns
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IDCT4x4_1D
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b end_vp9_iht4x4_16_add_neon
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iadst_iadst
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; generate constants
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GENERATE_SINE_CONSTANTS
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; first transform rows
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IADST4x4_1D
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; transpose the matrix
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TRANSPOSE4X4
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; then transform columns
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IADST4x4_1D
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end_vp9_iht4x4_16_add_neon
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; ROUND_POWER_OF_TWO(temp_out[j], 4)
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vrshr.s16 q8, q8, #4
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vrshr.s16 q9, q9, #4
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vld1.32 {d26[0]}, [r1], r2
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vld1.32 {d26[1]}, [r1], r2
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vld1.32 {d27[0]}, [r1], r2
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vld1.32 {d27[1]}, [r1]
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; ROUND_POWER_OF_TWO(temp_out[j], 4) + dest[j * dest_stride + i]
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vaddw.u8 q8, q8, d26
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vaddw.u8 q9, q9, d27
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; clip_pixel
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vqmovun.s16 d26, q8
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vqmovun.s16 d27, q9
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; do the stores in reverse order with negative post-increment, by changing
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; the sign of the stride
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rsb r2, r2, #0
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vst1.32 {d27[1]}, [r1], r2
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vst1.32 {d27[0]}, [r1], r2
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vst1.32 {d26[1]}, [r1], r2
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vst1.32 {d26[0]}, [r1] ; no post-increment
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bx lr
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ENDP ; |vp9_iht4x4_16_add_neon|
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END
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