0fa8b668c1
2 functions were optimized for avx2 by using full 256 bit register In order to handle 32 elements in parallel instead of only 16 in parallel: 1. vp9_sad32x32x4d 2. vp9_sad64x64x4d The function level gain is 66% and the user level gain is ~1%. Change-Id: I4efbb3bc7d8bc03b64b6c98f5cd5c4a9dd3212cb
168 lines
6.2 KiB
C
168 lines
6.2 KiB
C
/*
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* Copyright (c) 2014 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <immintrin.h> // AVX2
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#include "vpx/vpx_integer.h"
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void vp9_sad32x32x4d_avx2(uint8_t *src,
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int src_stride,
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uint8_t *ref[4],
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int ref_stride,
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unsigned int res[4]) {
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__m256i src_reg, ref0_reg, ref1_reg, ref2_reg, ref3_reg;
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__m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
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__m256i sum_mlow, sum_mhigh;
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int i;
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uint8_t *ref0, *ref1, *ref2, *ref3;
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ref0 = ref[0];
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ref1 = ref[1];
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ref2 = ref[2];
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ref3 = ref[3];
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sum_ref0 = _mm256_set1_epi16(0);
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sum_ref1 = _mm256_set1_epi16(0);
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sum_ref2 = _mm256_set1_epi16(0);
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sum_ref3 = _mm256_set1_epi16(0);
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for (i = 0; i < 32 ; i++) {
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// load src and all refs
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src_reg = _mm256_load_si256((__m256i *)(src));
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ref0_reg = _mm256_loadu_si256((__m256i *) (ref0));
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ref1_reg = _mm256_loadu_si256((__m256i *) (ref1));
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ref2_reg = _mm256_loadu_si256((__m256i *) (ref2));
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ref3_reg = _mm256_loadu_si256((__m256i *) (ref3));
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// sum of the absolute differences between every ref-i to src
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ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
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ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
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ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
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ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);
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// sum every ref-i
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sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
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sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
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sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
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sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
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src+= src_stride;
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ref0+= ref_stride;
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ref1+= ref_stride;
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ref2+= ref_stride;
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ref3+= ref_stride;
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}
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{
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__m128i sum;
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// in sum_ref-i the result is saved in the first 4 bytes
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// the other 4 bytes are zeroed.
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// sum_ref1 and sum_ref3 are shifted left by 4 bytes
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sum_ref1 = _mm256_slli_si256(sum_ref1, 4);
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sum_ref3 = _mm256_slli_si256(sum_ref3, 4);
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// merge sum_ref0 and sum_ref1 also sum_ref2 and sum_ref3
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sum_ref0 = _mm256_or_si256(sum_ref0, sum_ref1);
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sum_ref2 = _mm256_or_si256(sum_ref2, sum_ref3);
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// merge every 64 bit from each sum_ref-i
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sum_mlow = _mm256_unpacklo_epi64(sum_ref0, sum_ref2);
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sum_mhigh = _mm256_unpackhi_epi64(sum_ref0, sum_ref2);
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// add the low 64 bit to the high 64 bit
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sum_mlow = _mm256_add_epi32(sum_mlow, sum_mhigh);
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// add the low 128 bit to the high 128 bit
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sum = _mm_add_epi32(_mm256_castsi256_si128(sum_mlow),
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_mm256_extractf128_si256(sum_mlow, 1));
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_mm_storeu_si128((__m128i *)(res), sum);
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}
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}
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void vp9_sad64x64x4d_avx2(uint8_t *src,
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int src_stride,
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uint8_t *ref[4],
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int ref_stride,
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unsigned int res[4]) {
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__m256i src_reg, srcnext_reg, ref0_reg, ref0next_reg;
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__m256i ref1_reg, ref1next_reg, ref2_reg, ref2next_reg;
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__m256i ref3_reg, ref3next_reg;
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__m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
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__m256i sum_mlow, sum_mhigh;
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int i;
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uint8_t *ref0, *ref1, *ref2, *ref3;
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ref0 = ref[0];
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ref1 = ref[1];
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ref2 = ref[2];
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ref3 = ref[3];
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sum_ref0 = _mm256_set1_epi16(0);
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sum_ref1 = _mm256_set1_epi16(0);
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sum_ref2 = _mm256_set1_epi16(0);
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sum_ref3 = _mm256_set1_epi16(0);
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for (i = 0; i < 64 ; i++) {
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// load 64 bytes from src and all refs
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src_reg = _mm256_load_si256((__m256i *)(src));
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srcnext_reg = _mm256_load_si256((__m256i *)(src + 32));
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ref0_reg = _mm256_loadu_si256((__m256i *) (ref0));
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ref0next_reg = _mm256_loadu_si256((__m256i *) (ref0 + 32));
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ref1_reg = _mm256_loadu_si256((__m256i *) (ref1));
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ref1next_reg = _mm256_loadu_si256((__m256i *) (ref1 + 32));
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ref2_reg = _mm256_loadu_si256((__m256i *) (ref2));
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ref2next_reg = _mm256_loadu_si256((__m256i *) (ref2 + 32));
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ref3_reg = _mm256_loadu_si256((__m256i *) (ref3));
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ref3next_reg = _mm256_loadu_si256((__m256i *) (ref3 + 32));
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// sum of the absolute differences between every ref-i to src
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ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
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ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
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ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
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ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);
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ref0next_reg = _mm256_sad_epu8(ref0next_reg, srcnext_reg);
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ref1next_reg = _mm256_sad_epu8(ref1next_reg, srcnext_reg);
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ref2next_reg = _mm256_sad_epu8(ref2next_reg, srcnext_reg);
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ref3next_reg = _mm256_sad_epu8(ref3next_reg, srcnext_reg);
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// sum every ref-i
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sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
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sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
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sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
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sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
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sum_ref0 = _mm256_add_epi32(sum_ref0, ref0next_reg);
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sum_ref1 = _mm256_add_epi32(sum_ref1, ref1next_reg);
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sum_ref2 = _mm256_add_epi32(sum_ref2, ref2next_reg);
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sum_ref3 = _mm256_add_epi32(sum_ref3, ref3next_reg);
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src+= src_stride;
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ref0+= ref_stride;
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ref1+= ref_stride;
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ref2+= ref_stride;
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ref3+= ref_stride;
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}
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{
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__m128i sum;
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// in sum_ref-i the result is saved in the first 4 bytes
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// the other 4 bytes are zeroed.
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// sum_ref1 and sum_ref3 are shifted left by 4 bytes
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sum_ref1 = _mm256_slli_si256(sum_ref1, 4);
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sum_ref3 = _mm256_slli_si256(sum_ref3, 4);
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// merge sum_ref0 and sum_ref1 also sum_ref2 and sum_ref3
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sum_ref0 = _mm256_or_si256(sum_ref0, sum_ref1);
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sum_ref2 = _mm256_or_si256(sum_ref2, sum_ref3);
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// merge every 64 bit from each sum_ref-i
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sum_mlow = _mm256_unpacklo_epi64(sum_ref0, sum_ref2);
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sum_mhigh = _mm256_unpackhi_epi64(sum_ref0, sum_ref2);
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// add the low 64 bit to the high 64 bit
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sum_mlow = _mm256_add_epi32(sum_mlow, sum_mhigh);
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// add the low 128 bit to the high 128 bit
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sum = _mm_add_epi32(_mm256_castsi256_si128(sum_mlow),
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_mm256_extractf128_si256(sum_mlow, 1));
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_mm_storeu_si128((__m128i *)(res), sum);
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}
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}
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