b71962fdc9
The primary goal is to allow a binary to be built which supports NEON, but can fall back to non-NEON routines, since some Android devices do not have NEON, even if they are otherwise ARMv7 (e.g., Tegra). The configure-generated flags HAVE_ARMV7, etc., are used to decide which versions of each function to build, and when CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen at run time. In order for this to work, the CFLAGS must be set to something appropriate (e.g., without -mfpu=neon for ARMv7, and with appropriate -march and -mcpu for even earlier configurations), or the native C code will not be able to run. The ASFLAGS must remain set for the most advanced instruction set required at build time, since the ARM assembler will refuse to emit them otherwise. I have not attempted to make any changes to configure to do this automatically. Doing so will probably require the addition of new configure options. Many of the hooks for RTCD on ARM were already there, but a lot of the code had bit-rotted, and a good deal of the ARM-specific code is not integrated into the RTCD structs at all. I did not try to resolve the latter, merely to add the minimal amount of protection around them to allow RTCD to work. Those functions that were called based on an ifdef at the calling site were expanded to check the RTCD flags at that site, but they should be added to an RTCD struct somewhere in the future. The functions invoked with global function pointers still are, but these should be moved into an RTCD struct for thread safety (I believe every platform currently supported has atomic pointer stores, but this is not guaranteed). The encoder's boolhuff functions did not even have _c and armv7 suffixes, and the correct version was resolved at link time. The token packing functions did have appropriate suffixes, but the version was selected with a define, with no associated RTCD struct. However, for both of these, the only armv7 instruction they actually used was rbit, and this was completely superfluous, so I reworked them to avoid it. The only non-ARMv4 instruction remaining in them is clz, which is ARMv5 (not even ARMv5TE is required). Considering that there are no ARM-specific configs which are not at least ARMv5TE, I did not try to detect these at runtime, and simply enable them for ARMv5 and above. Finally, the NEON register saving code was completely non-reentrant, since it saved the registers to a global, static variable. I moved the storage for this onto the stack. A single binary built with this code was tested on an ARM11 (ARMv6) and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder, and produced identical output, while using the correct accelerated functions on each. I did not test on any earlier processors. Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
329 lines
11 KiB
NASM
329 lines
11 KiB
NASM
;
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vp8cx_pack_mb_row_tokens_armv5|
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INCLUDE vpx_vp8_enc_asm_offsets.asm
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ARM
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REQUIRE8
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PRESERVE8
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AREA |.text|, CODE, READONLY
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; r0 VP8_COMP *cpi
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; r1 vp8_writer *w
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; r2 vp8_coef_encodings
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; r3 vp8_extra_bits
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; s0 vp8_coef_tree
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|vp8cx_pack_mb_row_tokens_armv5| PROC
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push {r4-r11, lr}
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sub sp, sp, #24
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; Compute address of cpi->common.mb_rows
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ldr r4, _VP8_COMP_common_
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ldr r6, _VP8_COMMON_MBrows_
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add r4, r0, r4
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ldr r5, [r4, r6] ; load up mb_rows
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str r2, [sp, #20] ; save vp8_coef_encodings
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str r5, [sp, #12] ; save mb_rows
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str r3, [sp, #8] ; save vp8_extra_bits
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ldr r4, _VP8_COMP_tplist_
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add r4, r0, r4
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ldr r7, [r4, #0] ; dereference cpi->tp_list
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mov r0, r1 ; keep same as other loops
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ldr r2, [r0, #vp8_writer_lowvalue]
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ldr r5, [r0, #vp8_writer_range]
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ldr r3, [r0, #vp8_writer_count]
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mb_row_loop
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ldr r1, [r7, #tokenlist_start]
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ldr r9, [r7, #tokenlist_stop]
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str r9, [sp, #0] ; save stop for later comparison
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str r7, [sp, #16] ; tokenlist address for next time
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b check_p_lt_stop
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; actuall work gets done here!
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while_p_lt_stop
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ldr r6, [r1, #tokenextra_token] ; t
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ldr r4, [sp, #20] ; vp8_coef_encodings
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mov lr, #0
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add r4, r4, r6, lsl #3 ; a = vp8_coef_encodings + t
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ldr r9, [r1, #tokenextra_context_tree] ; pp
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ldr r7, [r1, #tokenextra_skip_eob_node]
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ldr r6, [r4, #vp8_token_value] ; v
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ldr r8, [r4, #vp8_token_len] ; n
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; vp8 specific skip_eob_node
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cmp r7, #0
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movne lr, #2 ; i = 2
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subne r8, r8, #1 ; --n
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rsb r4, r8, #32 ; 32-n
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ldr r10, [sp, #60] ; vp8_coef_tree
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; v is kept in r12 during the token pack loop
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lsl r12, r6, r4 ; r12 = v << 32 - n
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; loop start
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token_loop
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ldrb r4, [r9, lr, asr #1] ; pp [i>>1]
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sub r7, r5, #1 ; range-1
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; Decisions are made based on the bit value shifted
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; off of v, so set a flag here based on this.
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; This value is refered to as "bb"
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lsls r12, r12, #1 ; bb = v >> n
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mul r4, r4, r7 ; ((range-1) * pp[i>>1]))
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; bb can only be 0 or 1. So only execute this statement
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; if bb == 1, otherwise it will act like i + 0
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addcs lr, lr, #1 ; i + bb
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mov r7, #1
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ldrsb lr, [r10, lr] ; i = vp8_coef_tree[i+bb]
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add r4, r7, r4, lsr #8 ; 1 + (((range-1) * pp[i>>1]) >> 8)
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addcs r2, r2, r4 ; if (bb) lowvalue += split
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subcs r4, r5, r4 ; if (bb) range = range-split
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; Counting the leading zeros is used to normalize range.
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clz r6, r4
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sub r6, r6, #24 ; shift
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; Flag is set on the sum of count. This flag is used later
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; to determine if count >= 0
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adds r3, r3, r6 ; count += shift
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lsl r5, r4, r6 ; range <<= shift
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bmi token_count_lt_zero ; if(count >= 0)
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sub r6, r6, r3 ; offset = shift - count
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sub r4, r6, #1 ; offset-1
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lsls r4, r2, r4 ; if((lowvalue<<(offset-1)) & 0x80000000 )
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bpl token_high_bit_not_set
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ldr r4, [r0, #vp8_writer_pos] ; x
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sub r4, r4, #1 ; x = w->pos-1
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b token_zero_while_start
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token_zero_while_loop
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mov r10, #0
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strb r10, [r7, r4] ; w->buffer[x] =(unsigned char)0
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sub r4, r4, #1 ; x--
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token_zero_while_start
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cmp r4, #0
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ldrge r7, [r0, #vp8_writer_buffer]
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ldrb r11, [r7, r4]
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cmpge r11, #0xff
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beq token_zero_while_loop
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ldr r7, [r0, #vp8_writer_buffer]
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ldrb r10, [r7, r4] ; w->buffer[x]
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add r10, r10, #1
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strb r10, [r7, r4] ; w->buffer[x] + 1
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token_high_bit_not_set
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rsb r4, r6, #24 ; 24-offset
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ldr r10, [r0, #vp8_writer_buffer]
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lsr r7, r2, r4 ; lowvalue >> (24-offset)
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ldr r4, [r0, #vp8_writer_pos] ; w->pos
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lsl r2, r2, r6 ; lowvalue <<= offset
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mov r6, r3 ; shift = count
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add r11, r4, #1 ; w->pos++
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bic r2, r2, #0xff000000 ; lowvalue &= 0xffffff
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str r11, [r0, #vp8_writer_pos]
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sub r3, r3, #8 ; count -= 8
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strb r7, [r10, r4] ; w->buffer[w->pos++]
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; r10 is used earlier in the loop, but r10 is used as
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; temp variable here. So after r10 is used, reload
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; vp8_coef_tree_dcd into r10
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ldr r10, [sp, #60] ; vp8_coef_tree
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token_count_lt_zero
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lsl r2, r2, r6 ; lowvalue <<= shift
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subs r8, r8, #1 ; --n
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bne token_loop
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ldr r6, [r1, #tokenextra_token] ; t
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ldr r7, [sp, #8] ; vp8_extra_bits
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; Add t * sizeof (vp8_extra_bit_struct) to get the desired
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; element. Here vp8_extra_bit_struct == 20
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add r6, r6, r6, lsl #2 ; b = vp8_extra_bits + t
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add r12, r7, r6, lsl #2 ; b = vp8_extra_bits + t
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ldr r4, [r12, #vp8_extra_bit_struct_base_val]
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cmp r4, #0
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beq skip_extra_bits
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; if( b->base_val)
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ldr r8, [r12, #vp8_extra_bit_struct_len] ; L
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ldr lr, [r1, #tokenextra_extra] ; e = p->Extra
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cmp r8, #0 ; if( L)
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beq no_extra_bits
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ldr r9, [r12, #vp8_extra_bit_struct_prob]
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asr r7, lr, #1 ; v=e>>1
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ldr r10, [r12, #vp8_extra_bit_struct_tree]
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str r10, [sp, #4] ; b->tree
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rsb r4, r8, #32
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lsl r12, r7, r4
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mov lr, #0 ; i = 0
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extra_bits_loop
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ldrb r4, [r9, lr, asr #1] ; pp[i>>1]
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sub r7, r5, #1 ; range-1
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lsls r12, r12, #1 ; v >> n
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mul r4, r4, r7 ; (range-1) * pp[i>>1]
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addcs lr, lr, #1 ; i + bb
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mov r7, #1
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ldrsb lr, [r10, lr] ; i = b->tree[i+bb]
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add r4, r7, r4, lsr #8 ; split = 1 + (((range-1) * pp[i>>1]) >> 8)
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addcs r2, r2, r4 ; if (bb) lowvalue += split
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subcs r4, r5, r4 ; if (bb) range = range-split
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clz r6, r4
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sub r6, r6, #24
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adds r3, r3, r6 ; count += shift
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lsl r5, r4, r6 ; range <<= shift
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bmi extra_count_lt_zero ; if(count >= 0)
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sub r6, r6, r3 ; offset= shift - count
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sub r4, r6, #1 ; offset-1
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lsls r4, r2, r4 ; if((lowvalue<<(offset-1)) & 0x80000000 )
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bpl extra_high_bit_not_set
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ldr r4, [r0, #vp8_writer_pos] ; x
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sub r4, r4, #1 ; x = w->pos - 1
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b extra_zero_while_start
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extra_zero_while_loop
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mov r10, #0
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strb r10, [r7, r4] ; w->buffer[x] =(unsigned char)0
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sub r4, r4, #1 ; x--
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extra_zero_while_start
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cmp r4, #0
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ldrge r7, [r0, #vp8_writer_buffer]
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ldrb r11, [r7, r4]
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cmpge r11, #0xff
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beq extra_zero_while_loop
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ldr r7, [r0, #vp8_writer_buffer]
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ldrb r10, [r7, r4]
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add r10, r10, #1
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strb r10, [r7, r4]
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extra_high_bit_not_set
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rsb r4, r6, #24 ; 24-offset
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ldr r10, [r0, #vp8_writer_buffer]
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lsr r7, r2, r4 ; lowvalue >> (24-offset)
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ldr r4, [r0, #vp8_writer_pos]
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lsl r2, r2, r6 ; lowvalue <<= offset
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mov r6, r3 ; shift = count
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add r11, r4, #1 ; w->pos++
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bic r2, r2, #0xff000000 ; lowvalue &= 0xffffff
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str r11, [r0, #vp8_writer_pos]
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sub r3, r3, #8 ; count -= 8
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strb r7, [r10, r4] ; w->buffer[w->pos++]=(lowvalue >> (24-offset))
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ldr r10, [sp, #4] ; b->tree
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extra_count_lt_zero
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lsl r2, r2, r6
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subs r8, r8, #1 ; --n
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bne extra_bits_loop ; while (n)
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no_extra_bits
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ldr lr, [r1, #4] ; e = p->Extra
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add r4, r5, #1 ; range + 1
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tst lr, #1
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lsr r4, r4, #1 ; split = (range + 1) >> 1
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addne r2, r2, r4 ; lowvalue += split
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subne r4, r5, r4 ; range = range-split
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tst r2, #0x80000000 ; lowvalue & 0x80000000
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lsl r5, r4, #1 ; range <<= 1
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beq end_high_bit_not_set
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ldr r4, [r0, #vp8_writer_pos]
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mov r7, #0
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sub r4, r4, #1
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b end_zero_while_start
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end_zero_while_loop
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strb r7, [r6, r4]
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sub r4, r4, #1 ; x--
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end_zero_while_start
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cmp r4, #0
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ldrge r6, [r0, #vp8_writer_buffer]
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ldrb r12, [r6, r4]
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cmpge r12, #0xff
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beq end_zero_while_loop
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ldr r6, [r0, #vp8_writer_buffer]
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ldrb r7, [r6, r4]
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add r7, r7, #1
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strb r7, [r6, r4]
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end_high_bit_not_set
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adds r3, r3, #1 ; ++count
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lsl r2, r2, #1 ; lowvalue <<= 1
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bne end_count_zero
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ldr r4, [r0, #vp8_writer_pos]
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mvn r3, #7
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ldr r7, [r0, #vp8_writer_buffer]
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lsr r6, r2, #24 ; lowvalue >> 24
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add r12, r4, #1 ; w->pos++
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bic r2, r2, #0xff000000 ; lowvalue &= 0xffffff
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str r12, [r0, #0x10]
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strb r6, [r7, r4]
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end_count_zero
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skip_extra_bits
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add r1, r1, #TOKENEXTRA_SZ ; ++p
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check_p_lt_stop
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ldr r4, [sp, #0] ; stop
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cmp r1, r4 ; while( p < stop)
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bcc while_p_lt_stop
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ldr r6, [sp, #12] ; mb_rows
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ldr r7, [sp, #16] ; tokenlist address
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subs r6, r6, #1
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add r7, r7, #TOKENLIST_SZ ; next element in the array
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str r6, [sp, #12]
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bne mb_row_loop
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str r2, [r0, #vp8_writer_lowvalue]
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str r5, [r0, #vp8_writer_range]
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str r3, [r0, #vp8_writer_count]
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add sp, sp, #24
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pop {r4-r11, pc}
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ENDP
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_VP8_COMP_common_
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DCD vp8_comp_common
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_VP8_COMMON_MBrows_
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DCD vp8_common_mb_rows
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_VP8_COMP_tplist_
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DCD vp8_comp_tplist
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END
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