af7fb17c09
Function level timing test shows about 27% time saving on a Xeon E5-2680 v2 desktop. Rename vp9_dct_sse2.c to vp9_dct_intrin_sse2.c for vp9 and rename dct_sse2.c to dct_intrin_sse2.c for vp10 to avoid duplicate basenames. Actually vp9_fwht4x4_mmx/sse2() and vp10_fwht4x4_mmx/sse2() are identical. TODO: They should be unified later if there is no intention to keep a duplicate. Change-Id: I3e537b7bbd9ba417c606cd7c68c4dbbfa583f77d
88 lines
2.7 KiB
NASM
88 lines
2.7 KiB
NASM
;
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; Copyright (c) 2016 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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%define private_prefix vp9
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%include "third_party/x86inc/x86inc.asm"
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SECTION .text
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%macro TRANSFORM_COLS 0
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paddw m0, m1
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movq m4, m0
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psubw m3, m2
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psubw m4, m3
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psraw m4, 1
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movq m5, m4
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psubw m5, m1 ;b1
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psubw m4, m2 ;c1
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psubw m0, m4
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paddw m3, m5
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; m0 a0
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SWAP 1, 4 ; m1 c1
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SWAP 2, 3 ; m2 d1
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SWAP 3, 5 ; m3 b1
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%endmacro
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%macro TRANSPOSE_4X4 0
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; 00 01 02 03
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; 10 11 12 13
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; 20 21 22 23
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; 30 31 32 33
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punpcklwd m0, m1 ; 00 10 01 11 02 12 03 13
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punpcklwd m2, m3 ; 20 30 21 31 22 32 23 33
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mova m1, m0
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punpckldq m0, m2 ; 00 10 20 30 01 11 21 31
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punpckhdq m1, m2 ; 02 12 22 32 03 13 23 33
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%endmacro
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INIT_XMM sse2
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cglobal fwht4x4, 3, 4, 8, input, output, stride
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; TODO(linfeng): The duplication with vp10 should be resolved.
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lea r3q, [inputq + strideq*4]
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movq m0, [inputq] ;a1
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movq m1, [inputq + strideq*2] ;b1
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movq m2, [r3q] ;c1
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movq m3, [r3q + strideq*2] ;d1
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TRANSFORM_COLS
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TRANSPOSE_4X4
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SWAP 1, 2
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psrldq m1, m0, 8
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psrldq m3, m2, 8
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TRANSFORM_COLS
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TRANSPOSE_4X4
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psllw m0, 2
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psllw m1, 2
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%if CONFIG_VP9_HIGHBITDEPTH
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; sign extension
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mova m2, m0
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mova m3, m1
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punpcklwd m0, m0
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punpcklwd m1, m1
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punpckhwd m2, m2
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punpckhwd m3, m3
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psrad m0, 16
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psrad m1, 16
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psrad m2, 16
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psrad m3, 16
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mova [outputq], m0
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mova [outputq + 16], m2
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mova [outputq + 32], m1
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mova [outputq + 48], m3
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%else
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mova [outputq], m0
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mova [outputq + 16], m1
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%endif
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RET
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