260 lines
7.8 KiB
NASM
260 lines
7.8 KiB
NASM
;
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vp8_yv12_copy_src_frame_func_neon|
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ARM
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REQUIRE8
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PRESERVE8
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INCLUDE vpx_scale_asm_offsets.asm
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AREA ||.text||, CODE, READONLY, ALIGN=2
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;Note: This function is used to copy source data in src_buffer[i] at beginning
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;of the encoding. The buffer has a width and height of cpi->oxcf.Width and
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;cpi->oxcf.Height, which can be ANY numbers(NOT always multiples of 16 or 4).
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;void vp8_yv12_copy_src_frame_func_neon(const YV12_BUFFER_CONFIG *src_ybc,
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; YV12_BUFFER_CONFIG *dst_ybc);
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|vp8_yv12_copy_src_frame_func_neon| PROC
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push {r4 - r11, lr}
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vpush {d8 - d15}
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;Copy Y plane
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ldr r4, [r0, #yv12_buffer_config_y_height]
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ldr r5, [r0, #yv12_buffer_config_y_width]
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ldr r6, [r0, #yv12_buffer_config_y_stride]
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ldr r7, [r1, #yv12_buffer_config_y_stride]
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ldr r2, [r0, #yv12_buffer_config_y_buffer] ;srcptr1
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ldr r3, [r1, #yv12_buffer_config_y_buffer] ;dstptr1
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add r10, r2, r6 ;second row src
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add r11, r3, r7 ;second row dst
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mov r6, r6, lsl #1
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mov r7, r7, lsl #1
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sub r6, r6, r5 ;adjust stride
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sub r7, r7, r5
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; copy two rows at one time
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mov lr, r4, lsr #1
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cp_src_to_dst_height_loop
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mov r12, r5
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cp_width_128_loop
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vld1.8 {q0, q1}, [r2]!
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vld1.8 {q4, q5}, [r10]!
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vld1.8 {q2, q3}, [r2]!
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vld1.8 {q6, q7}, [r10]!
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vld1.8 {q8, q9}, [r2]!
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vld1.8 {q12, q13}, [r10]!
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vld1.8 {q10, q11}, [r2]!
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vld1.8 {q14, q15}, [r10]!
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sub r12, r12, #128
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cmp r12, #128
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vst1.8 {q0, q1}, [r3]!
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vst1.8 {q4, q5}, [r11]!
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vst1.8 {q2, q3}, [r3]!
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vst1.8 {q6, q7}, [r11]!
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vst1.8 {q8, q9}, [r3]!
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vst1.8 {q12, q13}, [r11]!
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vst1.8 {q10, q11}, [r3]!
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vst1.8 {q14, q15}, [r11]!
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bhs cp_width_128_loop
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cmp r12, #0
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beq cp_width_done
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cp_width_8_loop
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vld1.8 {d0}, [r2]!
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vld1.8 {d1}, [r10]!
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sub r12, r12, #8
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cmp r12, #8
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vst1.8 {d0}, [r3]!
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vst1.8 {d1}, [r11]!
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bhs cp_width_8_loop
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cmp r12, #0
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beq cp_width_done
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cp_width_1_loop
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ldrb r8, [r2], #1
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subs r12, r12, #1
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strb r8, [r3], #1
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ldrb r8, [r10], #1
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strb r8, [r11], #1
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bne cp_width_1_loop
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cp_width_done
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subs lr, lr, #1
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add r2, r2, r6
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add r3, r3, r7
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add r10, r10, r6
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add r11, r11, r7
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bne cp_src_to_dst_height_loop
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;copy last line for Y if y_height is odd
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tst r4, #1
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beq cp_width_done_1
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mov r12, r5
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cp_width_128_loop_1
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vld1.8 {q0, q1}, [r2]!
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vld1.8 {q2, q3}, [r2]!
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vld1.8 {q8, q9}, [r2]!
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vld1.8 {q10, q11}, [r2]!
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sub r12, r12, #128
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cmp r12, #128
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vst1.8 {q0, q1}, [r3]!
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vst1.8 {q2, q3}, [r3]!
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vst1.8 {q8, q9}, [r3]!
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vst1.8 {q10, q11}, [r3]!
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bhs cp_width_128_loop_1
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cmp r12, #0
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beq cp_width_done_1
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cp_width_8_loop_1
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vld1.8 {d0}, [r2]!
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sub r12, r12, #8
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cmp r12, #8
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vst1.8 {d0}, [r3]!
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bhs cp_width_8_loop_1
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cmp r12, #0
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beq cp_width_done_1
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cp_width_1_loop_1
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ldrb r8, [r2], #1
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subs r12, r12, #1
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strb r8, [r3], #1
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bne cp_width_1_loop_1
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cp_width_done_1
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;Copy U & V planes
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ldr r4, [r0, #yv12_buffer_config_uv_height]
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ldr r5, [r0, #yv12_buffer_config_uv_width]
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ldr r6, [r0, #yv12_buffer_config_uv_stride]
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ldr r7, [r1, #yv12_buffer_config_uv_stride]
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ldr r2, [r0, #yv12_buffer_config_u_buffer] ;srcptr1
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ldr r3, [r1, #yv12_buffer_config_u_buffer] ;dstptr1
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add r10, r2, r6 ;second row src
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add r11, r3, r7 ;second row dst
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mov r6, r6, lsl #1
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mov r7, r7, lsl #1
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sub r6, r6, r5 ;adjust stride
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sub r7, r7, r5
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mov r9, #2
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cp_uv_loop
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;copy two rows at one time
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mov lr, r4, lsr #1
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cp_src_to_dst_height_uv_loop
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mov r12, r5
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cp_width_uv_64_loop
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vld1.8 {q0, q1}, [r2]!
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vld1.8 {q4, q5}, [r10]!
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vld1.8 {q2, q3}, [r2]!
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vld1.8 {q6, q7}, [r10]!
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sub r12, r12, #64
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cmp r12, #64
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vst1.8 {q0, q1}, [r3]!
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vst1.8 {q4, q5}, [r11]!
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vst1.8 {q2, q3}, [r3]!
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vst1.8 {q6, q7}, [r11]!
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bhs cp_width_uv_64_loop
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cmp r12, #0
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beq cp_width_uv_done
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cp_width_uv_8_loop
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vld1.8 {d0}, [r2]!
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vld1.8 {d1}, [r10]!
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sub r12, r12, #8
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cmp r12, #8
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vst1.8 {d0}, [r3]!
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vst1.8 {d1}, [r11]!
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bhs cp_width_uv_8_loop
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cmp r12, #0
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beq cp_width_uv_done
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cp_width_uv_1_loop
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ldrb r8, [r2], #1
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subs r12, r12, #1
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strb r8, [r3], #1
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ldrb r8, [r10], #1
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strb r8, [r11], #1
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bne cp_width_uv_1_loop
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cp_width_uv_done
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subs lr, lr, #1
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add r2, r2, r6
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add r3, r3, r7
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add r10, r10, r6
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add r11, r11, r7
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bne cp_src_to_dst_height_uv_loop
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;copy last line for U & V if uv_height is odd
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tst r4, #1
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beq cp_width_uv_done_1
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mov r12, r5
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cp_width_uv_64_loop_1
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vld1.8 {q0, q1}, [r2]!
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vld1.8 {q2, q3}, [r2]!
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sub r12, r12, #64
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cmp r12, #64
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vst1.8 {q0, q1}, [r3]!
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vst1.8 {q2, q3}, [r3]!
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bhs cp_width_uv_64_loop_1
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cmp r12, #0
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beq cp_width_uv_done_1
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cp_width_uv_8_loop_1
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vld1.8 {d0}, [r2]!
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sub r12, r12, #8
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cmp r12, #8
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vst1.8 {d0}, [r3]!
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bhs cp_width_uv_8_loop_1
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cmp r12, #0
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beq cp_width_uv_done_1
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cp_width_uv_1_loop_1
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ldrb r8, [r2], #1
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subs r12, r12, #1
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strb r8, [r3], #1
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bne cp_width_uv_1_loop_1
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cp_width_uv_done_1
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subs r9, r9, #1
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ldrne r2, [r0, #yv12_buffer_config_v_buffer] ;srcptr1
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ldrne r3, [r1, #yv12_buffer_config_v_buffer] ;dstptr1
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ldrne r10, [r0, #yv12_buffer_config_uv_stride]
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ldrne r11, [r1, #yv12_buffer_config_uv_stride]
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addne r10, r2, r10 ;second row src
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addne r11, r3, r11 ;second row dst
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bne cp_uv_loop
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vpop {d8 - d15}
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pop {r4 - r11, pc}
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ENDP
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END
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