33df6d1fc1
The recent compiler can generate optimized code that uses NEON registers for various operations besides floating-point operations. Therefore, only saving callee-saved registers d8 - d15 at the beginning of the encoder/decoder is not enough anymore. This patch added register saving code in VP8 NEON functions that use those registers. Change-Id: Ie9e44f5188cf410990c8aaaac68faceee9dffd31
206 lines
6.3 KiB
NASM
206 lines
6.3 KiB
NASM
;
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vp8_subtract_b_neon|
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EXPORT |vp8_subtract_mby_neon|
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EXPORT |vp8_subtract_mbuv_neon|
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INCLUDE vp8_asm_enc_offsets.asm
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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;void vp8_subtract_b_neon(BLOCK *be, BLOCKD *bd, int pitch)
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|vp8_subtract_b_neon| PROC
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stmfd sp!, {r4-r7}
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ldr r3, [r0, #vp8_block_base_src]
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ldr r4, [r0, #vp8_block_src]
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ldr r5, [r0, #vp8_block_src_diff]
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ldr r3, [r3]
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ldr r6, [r0, #vp8_block_src_stride]
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add r3, r3, r4 ; src = *base_src + src
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ldr r7, [r1, #vp8_blockd_predictor]
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vld1.8 {d0}, [r3], r6 ;load src
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vld1.8 {d1}, [r7], r2 ;load pred
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vld1.8 {d2}, [r3], r6
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vld1.8 {d3}, [r7], r2
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vld1.8 {d4}, [r3], r6
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vld1.8 {d5}, [r7], r2
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vld1.8 {d6}, [r3], r6
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vld1.8 {d7}, [r7], r2
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vsubl.u8 q10, d0, d1
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vsubl.u8 q11, d2, d3
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vsubl.u8 q12, d4, d5
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vsubl.u8 q13, d6, d7
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mov r2, r2, lsl #1
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vst1.16 {d20}, [r5], r2 ;store diff
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vst1.16 {d22}, [r5], r2
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vst1.16 {d24}, [r5], r2
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vst1.16 {d26}, [r5], r2
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ldmfd sp!, {r4-r7}
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bx lr
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ENDP
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;==========================================
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;void vp8_subtract_mby_neon(short *diff, unsigned char *src, int src_stride
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; unsigned char *pred, int pred_stride)
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|vp8_subtract_mby_neon| PROC
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push {r4-r7}
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vpush {d8-d15}
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mov r12, #4
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ldr r4, [sp, #80] ; pred_stride
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mov r6, #32 ; "diff" stride x2
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add r5, r0, #16 ; second diff pointer
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subtract_mby_loop
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vld1.8 {q0}, [r1], r2 ;load src
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vld1.8 {q1}, [r3], r4 ;load pred
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vld1.8 {q2}, [r1], r2
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vld1.8 {q3}, [r3], r4
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vld1.8 {q4}, [r1], r2
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vld1.8 {q5}, [r3], r4
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vld1.8 {q6}, [r1], r2
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vld1.8 {q7}, [r3], r4
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vsubl.u8 q8, d0, d2
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vsubl.u8 q9, d1, d3
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vsubl.u8 q10, d4, d6
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vsubl.u8 q11, d5, d7
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vsubl.u8 q12, d8, d10
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vsubl.u8 q13, d9, d11
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vsubl.u8 q14, d12, d14
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vsubl.u8 q15, d13, d15
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vst1.16 {q8}, [r0], r6 ;store diff
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vst1.16 {q9}, [r5], r6
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vst1.16 {q10}, [r0], r6
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vst1.16 {q11}, [r5], r6
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vst1.16 {q12}, [r0], r6
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vst1.16 {q13}, [r5], r6
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vst1.16 {q14}, [r0], r6
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vst1.16 {q15}, [r5], r6
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subs r12, r12, #1
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bne subtract_mby_loop
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vpop {d8-d15}
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pop {r4-r7}
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bx lr
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ENDP
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;=================================
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;void vp8_subtract_mbuv_c(short *diff, unsigned char *usrc, unsigned char *vsrc,
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; int src_stride, unsigned char *upred,
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; unsigned char *vpred, int pred_stride)
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|vp8_subtract_mbuv_neon| PROC
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push {r4-r7}
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vpush {d8-d15}
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ldr r4, [sp, #80] ; upred
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ldr r5, [sp, #84] ; vpred
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ldr r6, [sp, #88] ; pred_stride
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add r0, r0, #512 ; short *udiff = diff + 256;
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mov r12, #32 ; "diff" stride x2
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add r7, r0, #16 ; second diff pointer
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;u
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vld1.8 {d0}, [r1], r3 ;load usrc
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vld1.8 {d1}, [r4], r6 ;load upred
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vld1.8 {d2}, [r1], r3
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vld1.8 {d3}, [r4], r6
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vld1.8 {d4}, [r1], r3
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vld1.8 {d5}, [r4], r6
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vld1.8 {d6}, [r1], r3
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vld1.8 {d7}, [r4], r6
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vld1.8 {d8}, [r1], r3
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vld1.8 {d9}, [r4], r6
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vld1.8 {d10}, [r1], r3
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vld1.8 {d11}, [r4], r6
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vld1.8 {d12}, [r1], r3
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vld1.8 {d13}, [r4], r6
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vld1.8 {d14}, [r1], r3
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vld1.8 {d15}, [r4], r6
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vsubl.u8 q8, d0, d1
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vsubl.u8 q9, d2, d3
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vsubl.u8 q10, d4, d5
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vsubl.u8 q11, d6, d7
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vsubl.u8 q12, d8, d9
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vsubl.u8 q13, d10, d11
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vsubl.u8 q14, d12, d13
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vsubl.u8 q15, d14, d15
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vst1.16 {q8}, [r0], r12 ;store diff
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vst1.16 {q9}, [r7], r12
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vst1.16 {q10}, [r0], r12
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vst1.16 {q11}, [r7], r12
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vst1.16 {q12}, [r0], r12
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vst1.16 {q13}, [r7], r12
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vst1.16 {q14}, [r0], r12
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vst1.16 {q15}, [r7], r12
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;v
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vld1.8 {d0}, [r2], r3 ;load vsrc
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vld1.8 {d1}, [r5], r6 ;load vpred
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vld1.8 {d2}, [r2], r3
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vld1.8 {d3}, [r5], r6
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vld1.8 {d4}, [r2], r3
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vld1.8 {d5}, [r5], r6
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vld1.8 {d6}, [r2], r3
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vld1.8 {d7}, [r5], r6
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vld1.8 {d8}, [r2], r3
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vld1.8 {d9}, [r5], r6
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vld1.8 {d10}, [r2], r3
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vld1.8 {d11}, [r5], r6
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vld1.8 {d12}, [r2], r3
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vld1.8 {d13}, [r5], r6
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vld1.8 {d14}, [r2], r3
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vld1.8 {d15}, [r5], r6
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vsubl.u8 q8, d0, d1
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vsubl.u8 q9, d2, d3
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vsubl.u8 q10, d4, d5
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vsubl.u8 q11, d6, d7
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vsubl.u8 q12, d8, d9
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vsubl.u8 q13, d10, d11
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vsubl.u8 q14, d12, d13
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vsubl.u8 q15, d14, d15
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vst1.16 {q8}, [r0], r12 ;store diff
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vst1.16 {q9}, [r7], r12
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vst1.16 {q10}, [r0], r12
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vst1.16 {q11}, [r7], r12
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vst1.16 {q12}, [r0], r12
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vst1.16 {q13}, [r7], r12
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vst1.16 {q14}, [r0], r12
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vst1.16 {q15}, [r7], r12
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vpop {d8-d15}
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pop {r4-r7}
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bx lr
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ENDP
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END
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