728 lines
27 KiB
C
728 lines
27 KiB
C
/*
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* Copyright (c) 2012 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <immintrin.h> // AVX2
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#include "./vpx_dsp_rtcd.h"
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#include "vpx_ports/mem.h"
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DECLARE_ALIGNED(32, static const uint8_t, bilinear_filters_avx2[512]) = {
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16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0,
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16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0, 16, 0,
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14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2,
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14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2,
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12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4,
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12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4,
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10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6,
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10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6,
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8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
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8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
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6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10,
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6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10, 6, 10,
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4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12,
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4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12, 4, 12,
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2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14,
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2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14, 2, 14,
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};
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void vpx_get16x16var_avx2(const unsigned char *src_ptr,
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int source_stride,
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const unsigned char *ref_ptr,
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int recon_stride,
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unsigned int *SSE,
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int *Sum) {
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__m256i src, src_expand_low, src_expand_high, ref, ref_expand_low;
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__m256i ref_expand_high, madd_low, madd_high;
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unsigned int i, src_2strides, ref_2strides;
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__m256i zero_reg = _mm256_set1_epi16(0);
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__m256i sum_ref_src = _mm256_set1_epi16(0);
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__m256i madd_ref_src = _mm256_set1_epi16(0);
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// processing two strides in a 256 bit register reducing the number
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// of loop stride by half (comparing to the sse2 code)
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src_2strides = source_stride << 1;
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ref_2strides = recon_stride << 1;
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for (i = 0; i < 8; i++) {
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src = _mm256_castsi128_si256(
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_mm_loadu_si128((__m128i const *) (src_ptr)));
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src = _mm256_inserti128_si256(src,
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_mm_loadu_si128((__m128i const *)(src_ptr+source_stride)), 1);
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ref =_mm256_castsi128_si256(
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_mm_loadu_si128((__m128i const *) (ref_ptr)));
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ref = _mm256_inserti128_si256(ref,
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_mm_loadu_si128((__m128i const *)(ref_ptr+recon_stride)), 1);
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// expanding to 16 bit each lane
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src_expand_low = _mm256_unpacklo_epi8(src, zero_reg);
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src_expand_high = _mm256_unpackhi_epi8(src, zero_reg);
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ref_expand_low = _mm256_unpacklo_epi8(ref, zero_reg);
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ref_expand_high = _mm256_unpackhi_epi8(ref, zero_reg);
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// src-ref
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src_expand_low = _mm256_sub_epi16(src_expand_low, ref_expand_low);
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src_expand_high = _mm256_sub_epi16(src_expand_high, ref_expand_high);
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// madd low (src - ref)
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madd_low = _mm256_madd_epi16(src_expand_low, src_expand_low);
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// add high to low
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src_expand_low = _mm256_add_epi16(src_expand_low, src_expand_high);
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// madd high (src - ref)
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madd_high = _mm256_madd_epi16(src_expand_high, src_expand_high);
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sum_ref_src = _mm256_add_epi16(sum_ref_src, src_expand_low);
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// add high to low
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madd_ref_src = _mm256_add_epi32(madd_ref_src,
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_mm256_add_epi32(madd_low, madd_high));
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src_ptr+= src_2strides;
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ref_ptr+= ref_2strides;
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}
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{
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__m128i sum_res, madd_res;
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__m128i expand_sum_low, expand_sum_high, expand_sum;
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__m128i expand_madd_low, expand_madd_high, expand_madd;
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__m128i ex_expand_sum_low, ex_expand_sum_high, ex_expand_sum;
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// extract the low lane and add it to the high lane
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sum_res = _mm_add_epi16(_mm256_castsi256_si128(sum_ref_src),
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_mm256_extractf128_si256(sum_ref_src, 1));
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madd_res = _mm_add_epi32(_mm256_castsi256_si128(madd_ref_src),
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_mm256_extractf128_si256(madd_ref_src, 1));
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// padding each 2 bytes with another 2 zeroed bytes
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expand_sum_low = _mm_unpacklo_epi16(_mm256_castsi256_si128(zero_reg),
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sum_res);
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expand_sum_high = _mm_unpackhi_epi16(_mm256_castsi256_si128(zero_reg),
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sum_res);
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// shifting the sign 16 bits right
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expand_sum_low = _mm_srai_epi32(expand_sum_low, 16);
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expand_sum_high = _mm_srai_epi32(expand_sum_high, 16);
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expand_sum = _mm_add_epi32(expand_sum_low, expand_sum_high);
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// expand each 32 bits of the madd result to 64 bits
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expand_madd_low = _mm_unpacklo_epi32(madd_res,
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_mm256_castsi256_si128(zero_reg));
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expand_madd_high = _mm_unpackhi_epi32(madd_res,
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_mm256_castsi256_si128(zero_reg));
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expand_madd = _mm_add_epi32(expand_madd_low, expand_madd_high);
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ex_expand_sum_low = _mm_unpacklo_epi32(expand_sum,
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_mm256_castsi256_si128(zero_reg));
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ex_expand_sum_high = _mm_unpackhi_epi32(expand_sum,
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_mm256_castsi256_si128(zero_reg));
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ex_expand_sum = _mm_add_epi32(ex_expand_sum_low, ex_expand_sum_high);
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// shift 8 bytes eight
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madd_res = _mm_srli_si128(expand_madd, 8);
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sum_res = _mm_srli_si128(ex_expand_sum, 8);
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madd_res = _mm_add_epi32(madd_res, expand_madd);
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sum_res = _mm_add_epi32(sum_res, ex_expand_sum);
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*((int*)SSE)= _mm_cvtsi128_si32(madd_res);
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*((int*)Sum)= _mm_cvtsi128_si32(sum_res);
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}
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}
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void vpx_get32x32var_avx2(const unsigned char *src_ptr,
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int source_stride,
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const unsigned char *ref_ptr,
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int recon_stride,
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unsigned int *SSE,
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int *Sum) {
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__m256i src, src_expand_low, src_expand_high, ref, ref_expand_low;
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__m256i ref_expand_high, madd_low, madd_high;
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unsigned int i;
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__m256i zero_reg = _mm256_set1_epi16(0);
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__m256i sum_ref_src = _mm256_set1_epi16(0);
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__m256i madd_ref_src = _mm256_set1_epi16(0);
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// processing 32 elements in parallel
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for (i = 0; i < 16; i++) {
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src = _mm256_loadu_si256((__m256i const *) (src_ptr));
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ref = _mm256_loadu_si256((__m256i const *) (ref_ptr));
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// expanding to 16 bit each lane
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src_expand_low = _mm256_unpacklo_epi8(src, zero_reg);
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src_expand_high = _mm256_unpackhi_epi8(src, zero_reg);
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ref_expand_low = _mm256_unpacklo_epi8(ref, zero_reg);
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ref_expand_high = _mm256_unpackhi_epi8(ref, zero_reg);
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// src-ref
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src_expand_low = _mm256_sub_epi16(src_expand_low, ref_expand_low);
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src_expand_high = _mm256_sub_epi16(src_expand_high, ref_expand_high);
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// madd low (src - ref)
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madd_low = _mm256_madd_epi16(src_expand_low, src_expand_low);
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// add high to low
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src_expand_low = _mm256_add_epi16(src_expand_low, src_expand_high);
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// madd high (src - ref)
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madd_high = _mm256_madd_epi16(src_expand_high, src_expand_high);
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sum_ref_src = _mm256_add_epi16(sum_ref_src, src_expand_low);
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// add high to low
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madd_ref_src = _mm256_add_epi32(madd_ref_src,
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_mm256_add_epi32(madd_low, madd_high));
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src_ptr+= source_stride;
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ref_ptr+= recon_stride;
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}
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{
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__m256i expand_sum_low, expand_sum_high, expand_sum;
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__m256i expand_madd_low, expand_madd_high, expand_madd;
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__m256i ex_expand_sum_low, ex_expand_sum_high, ex_expand_sum;
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// padding each 2 bytes with another 2 zeroed bytes
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expand_sum_low = _mm256_unpacklo_epi16(zero_reg, sum_ref_src);
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expand_sum_high = _mm256_unpackhi_epi16(zero_reg, sum_ref_src);
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// shifting the sign 16 bits right
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expand_sum_low = _mm256_srai_epi32(expand_sum_low, 16);
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expand_sum_high = _mm256_srai_epi32(expand_sum_high, 16);
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expand_sum = _mm256_add_epi32(expand_sum_low, expand_sum_high);
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// expand each 32 bits of the madd result to 64 bits
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expand_madd_low = _mm256_unpacklo_epi32(madd_ref_src, zero_reg);
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expand_madd_high = _mm256_unpackhi_epi32(madd_ref_src, zero_reg);
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expand_madd = _mm256_add_epi32(expand_madd_low, expand_madd_high);
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ex_expand_sum_low = _mm256_unpacklo_epi32(expand_sum, zero_reg);
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ex_expand_sum_high = _mm256_unpackhi_epi32(expand_sum, zero_reg);
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ex_expand_sum = _mm256_add_epi32(ex_expand_sum_low, ex_expand_sum_high);
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// shift 8 bytes eight
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madd_ref_src = _mm256_srli_si256(expand_madd, 8);
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sum_ref_src = _mm256_srli_si256(ex_expand_sum, 8);
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madd_ref_src = _mm256_add_epi32(madd_ref_src, expand_madd);
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sum_ref_src = _mm256_add_epi32(sum_ref_src, ex_expand_sum);
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// extract the low lane and the high lane and add the results
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*((int*)SSE)= _mm_cvtsi128_si32(_mm256_castsi256_si128(madd_ref_src)) +
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_mm_cvtsi128_si32(_mm256_extractf128_si256(madd_ref_src, 1));
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*((int*)Sum)= _mm_cvtsi128_si32(_mm256_castsi256_si128(sum_ref_src)) +
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_mm_cvtsi128_si32(_mm256_extractf128_si256(sum_ref_src, 1));
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}
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}
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#define FILTER_SRC(filter) \
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/* filter the source */ \
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exp_src_lo = _mm256_maddubs_epi16(exp_src_lo, filter); \
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exp_src_hi = _mm256_maddubs_epi16(exp_src_hi, filter); \
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\
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/* add 8 to source */ \
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exp_src_lo = _mm256_add_epi16(exp_src_lo, pw8); \
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exp_src_hi = _mm256_add_epi16(exp_src_hi, pw8); \
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\
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/* divide source by 16 */ \
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exp_src_lo = _mm256_srai_epi16(exp_src_lo, 4); \
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exp_src_hi = _mm256_srai_epi16(exp_src_hi, 4);
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#define MERGE_WITH_SRC(src_reg, reg) \
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exp_src_lo = _mm256_unpacklo_epi8(src_reg, reg); \
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exp_src_hi = _mm256_unpackhi_epi8(src_reg, reg);
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#define LOAD_SRC_DST \
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/* load source and destination */ \
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src_reg = _mm256_loadu_si256((__m256i const *) (src)); \
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dst_reg = _mm256_loadu_si256((__m256i const *) (dst));
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#define AVG_NEXT_SRC(src_reg, size_stride) \
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src_next_reg = _mm256_loadu_si256((__m256i const *) \
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(src + size_stride)); \
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/* average between current and next stride source */ \
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src_reg = _mm256_avg_epu8(src_reg, src_next_reg);
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#define MERGE_NEXT_SRC(src_reg, size_stride) \
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src_next_reg = _mm256_loadu_si256((__m256i const *) \
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(src + size_stride)); \
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MERGE_WITH_SRC(src_reg, src_next_reg)
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#define CALC_SUM_SSE_INSIDE_LOOP \
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/* expand each byte to 2 bytes */ \
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exp_dst_lo = _mm256_unpacklo_epi8(dst_reg, zero_reg); \
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exp_dst_hi = _mm256_unpackhi_epi8(dst_reg, zero_reg); \
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/* source - dest */ \
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exp_src_lo = _mm256_sub_epi16(exp_src_lo, exp_dst_lo); \
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exp_src_hi = _mm256_sub_epi16(exp_src_hi, exp_dst_hi); \
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/* caculate sum */ \
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sum_reg = _mm256_add_epi16(sum_reg, exp_src_lo); \
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exp_src_lo = _mm256_madd_epi16(exp_src_lo, exp_src_lo); \
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sum_reg = _mm256_add_epi16(sum_reg, exp_src_hi); \
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exp_src_hi = _mm256_madd_epi16(exp_src_hi, exp_src_hi); \
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/* calculate sse */ \
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sse_reg = _mm256_add_epi32(sse_reg, exp_src_lo); \
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sse_reg = _mm256_add_epi32(sse_reg, exp_src_hi);
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// final calculation to sum and sse
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#define CALC_SUM_AND_SSE \
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res_cmp = _mm256_cmpgt_epi16(zero_reg, sum_reg); \
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sse_reg_hi = _mm256_srli_si256(sse_reg, 8); \
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sum_reg_lo = _mm256_unpacklo_epi16(sum_reg, res_cmp); \
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sum_reg_hi = _mm256_unpackhi_epi16(sum_reg, res_cmp); \
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sse_reg = _mm256_add_epi32(sse_reg, sse_reg_hi); \
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sum_reg = _mm256_add_epi32(sum_reg_lo, sum_reg_hi); \
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\
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sse_reg_hi = _mm256_srli_si256(sse_reg, 4); \
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sum_reg_hi = _mm256_srli_si256(sum_reg, 8); \
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\
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sse_reg = _mm256_add_epi32(sse_reg, sse_reg_hi); \
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sum_reg = _mm256_add_epi32(sum_reg, sum_reg_hi); \
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*((int*)sse)= _mm_cvtsi128_si32(_mm256_castsi256_si128(sse_reg)) + \
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_mm_cvtsi128_si32(_mm256_extractf128_si256(sse_reg, 1)); \
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sum_reg_hi = _mm256_srli_si256(sum_reg, 4); \
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sum_reg = _mm256_add_epi32(sum_reg, sum_reg_hi); \
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sum = _mm_cvtsi128_si32(_mm256_castsi256_si128(sum_reg)) + \
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_mm_cvtsi128_si32(_mm256_extractf128_si256(sum_reg, 1));
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unsigned int vpx_sub_pixel_variance32xh_avx2(const uint8_t *src,
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int src_stride,
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int x_offset,
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int y_offset,
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const uint8_t *dst,
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int dst_stride,
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int height,
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unsigned int *sse) {
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__m256i src_reg, dst_reg, exp_src_lo, exp_src_hi, exp_dst_lo, exp_dst_hi;
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__m256i sse_reg, sum_reg, sse_reg_hi, res_cmp, sum_reg_lo, sum_reg_hi;
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__m256i zero_reg;
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int i, sum;
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sum_reg = _mm256_set1_epi16(0);
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sse_reg = _mm256_set1_epi16(0);
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zero_reg = _mm256_set1_epi16(0);
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// x_offset = 0 and y_offset = 0
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if (x_offset == 0) {
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if (y_offset == 0) {
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for (i = 0; i < height ; i++) {
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LOAD_SRC_DST
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// expend each byte to 2 bytes
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MERGE_WITH_SRC(src_reg, zero_reg)
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CALC_SUM_SSE_INSIDE_LOOP
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src+= src_stride;
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dst+= dst_stride;
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}
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// x_offset = 0 and y_offset = 8
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} else if (y_offset == 8) {
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__m256i src_next_reg;
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for (i = 0; i < height ; i++) {
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LOAD_SRC_DST
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AVG_NEXT_SRC(src_reg, src_stride)
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// expend each byte to 2 bytes
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MERGE_WITH_SRC(src_reg, zero_reg)
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CALC_SUM_SSE_INSIDE_LOOP
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src+= src_stride;
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dst+= dst_stride;
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}
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// x_offset = 0 and y_offset = bilin interpolation
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} else {
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__m256i filter, pw8, src_next_reg;
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y_offset <<= 5;
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filter = _mm256_load_si256((__m256i const *)
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(bilinear_filters_avx2 + y_offset));
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pw8 = _mm256_set1_epi16(8);
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for (i = 0; i < height ; i++) {
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LOAD_SRC_DST
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MERGE_NEXT_SRC(src_reg, src_stride)
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FILTER_SRC(filter)
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CALC_SUM_SSE_INSIDE_LOOP
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src+= src_stride;
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dst+= dst_stride;
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}
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}
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// x_offset = 8 and y_offset = 0
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} else if (x_offset == 8) {
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if (y_offset == 0) {
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__m256i src_next_reg;
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for (i = 0; i < height ; i++) {
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LOAD_SRC_DST
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AVG_NEXT_SRC(src_reg, 1)
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// expand each byte to 2 bytes
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MERGE_WITH_SRC(src_reg, zero_reg)
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CALC_SUM_SSE_INSIDE_LOOP
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src+= src_stride;
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dst+= dst_stride;
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}
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// x_offset = 8 and y_offset = 8
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} else if (y_offset == 8) {
|
|
__m256i src_next_reg, src_avg;
|
|
// load source and another source starting from the next
|
|
// following byte
|
|
src_reg = _mm256_loadu_si256((__m256i const *) (src));
|
|
AVG_NEXT_SRC(src_reg, 1)
|
|
for (i = 0; i < height ; i++) {
|
|
src_avg = src_reg;
|
|
src+= src_stride;
|
|
LOAD_SRC_DST
|
|
AVG_NEXT_SRC(src_reg, 1)
|
|
// average between previous average to current average
|
|
src_avg = _mm256_avg_epu8(src_avg, src_reg);
|
|
// expand each byte to 2 bytes
|
|
MERGE_WITH_SRC(src_avg, zero_reg)
|
|
// save current source average
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
dst+= dst_stride;
|
|
}
|
|
// x_offset = 8 and y_offset = bilin interpolation
|
|
} else {
|
|
__m256i filter, pw8, src_next_reg, src_avg;
|
|
y_offset <<= 5;
|
|
filter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + y_offset));
|
|
pw8 = _mm256_set1_epi16(8);
|
|
// load source and another source starting from the next
|
|
// following byte
|
|
src_reg = _mm256_loadu_si256((__m256i const *) (src));
|
|
AVG_NEXT_SRC(src_reg, 1)
|
|
for (i = 0; i < height ; i++) {
|
|
// save current source average
|
|
src_avg = src_reg;
|
|
src+= src_stride;
|
|
LOAD_SRC_DST
|
|
AVG_NEXT_SRC(src_reg, 1)
|
|
MERGE_WITH_SRC(src_avg, src_reg)
|
|
FILTER_SRC(filter)
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
dst+= dst_stride;
|
|
}
|
|
}
|
|
// x_offset = bilin interpolation and y_offset = 0
|
|
} else {
|
|
if (y_offset == 0) {
|
|
__m256i filter, pw8, src_next_reg;
|
|
x_offset <<= 5;
|
|
filter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + x_offset));
|
|
pw8 = _mm256_set1_epi16(8);
|
|
for (i = 0; i < height ; i++) {
|
|
LOAD_SRC_DST
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
FILTER_SRC(filter)
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
src+= src_stride;
|
|
dst+= dst_stride;
|
|
}
|
|
// x_offset = bilin interpolation and y_offset = 8
|
|
} else if (y_offset == 8) {
|
|
__m256i filter, pw8, src_next_reg, src_pack;
|
|
x_offset <<= 5;
|
|
filter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + x_offset));
|
|
pw8 = _mm256_set1_epi16(8);
|
|
src_reg = _mm256_loadu_si256((__m256i const *) (src));
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
FILTER_SRC(filter)
|
|
// convert each 16 bit to 8 bit to each low and high lane source
|
|
src_pack = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
for (i = 0; i < height ; i++) {
|
|
src+= src_stride;
|
|
LOAD_SRC_DST
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
FILTER_SRC(filter)
|
|
src_reg = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
// average between previous pack to the current
|
|
src_pack = _mm256_avg_epu8(src_pack, src_reg);
|
|
MERGE_WITH_SRC(src_pack, zero_reg)
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
src_pack = src_reg;
|
|
dst+= dst_stride;
|
|
}
|
|
// x_offset = bilin interpolation and y_offset = bilin interpolation
|
|
} else {
|
|
__m256i xfilter, yfilter, pw8, src_next_reg, src_pack;
|
|
x_offset <<= 5;
|
|
xfilter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + x_offset));
|
|
y_offset <<= 5;
|
|
yfilter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + y_offset));
|
|
pw8 = _mm256_set1_epi16(8);
|
|
// load source and another source starting from the next
|
|
// following byte
|
|
src_reg = _mm256_loadu_si256((__m256i const *) (src));
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
|
|
FILTER_SRC(xfilter)
|
|
// convert each 16 bit to 8 bit to each low and high lane source
|
|
src_pack = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
for (i = 0; i < height ; i++) {
|
|
src+= src_stride;
|
|
LOAD_SRC_DST
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
FILTER_SRC(xfilter)
|
|
src_reg = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
// merge previous pack to current pack source
|
|
MERGE_WITH_SRC(src_pack, src_reg)
|
|
// filter the source
|
|
FILTER_SRC(yfilter)
|
|
src_pack = src_reg;
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
dst+= dst_stride;
|
|
}
|
|
}
|
|
}
|
|
CALC_SUM_AND_SSE
|
|
return sum;
|
|
}
|
|
|
|
unsigned int vpx_sub_pixel_avg_variance32xh_avx2(const uint8_t *src,
|
|
int src_stride,
|
|
int x_offset,
|
|
int y_offset,
|
|
const uint8_t *dst,
|
|
int dst_stride,
|
|
const uint8_t *sec,
|
|
int sec_stride,
|
|
int height,
|
|
unsigned int *sse) {
|
|
__m256i sec_reg;
|
|
__m256i src_reg, dst_reg, exp_src_lo, exp_src_hi, exp_dst_lo, exp_dst_hi;
|
|
__m256i sse_reg, sum_reg, sse_reg_hi, res_cmp, sum_reg_lo, sum_reg_hi;
|
|
__m256i zero_reg;
|
|
int i, sum;
|
|
sum_reg = _mm256_set1_epi16(0);
|
|
sse_reg = _mm256_set1_epi16(0);
|
|
zero_reg = _mm256_set1_epi16(0);
|
|
|
|
// x_offset = 0 and y_offset = 0
|
|
if (x_offset == 0) {
|
|
if (y_offset == 0) {
|
|
for (i = 0; i < height ; i++) {
|
|
LOAD_SRC_DST
|
|
sec_reg = _mm256_loadu_si256((__m256i const *) (sec));
|
|
src_reg = _mm256_avg_epu8(src_reg, sec_reg);
|
|
sec+= sec_stride;
|
|
// expend each byte to 2 bytes
|
|
MERGE_WITH_SRC(src_reg, zero_reg)
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
src+= src_stride;
|
|
dst+= dst_stride;
|
|
}
|
|
} else if (y_offset == 8) {
|
|
__m256i src_next_reg;
|
|
for (i = 0; i < height ; i++) {
|
|
LOAD_SRC_DST
|
|
AVG_NEXT_SRC(src_reg, src_stride)
|
|
sec_reg = _mm256_loadu_si256((__m256i const *) (sec));
|
|
src_reg = _mm256_avg_epu8(src_reg, sec_reg);
|
|
sec+= sec_stride;
|
|
// expend each byte to 2 bytes
|
|
MERGE_WITH_SRC(src_reg, zero_reg)
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
src+= src_stride;
|
|
dst+= dst_stride;
|
|
}
|
|
// x_offset = 0 and y_offset = bilin interpolation
|
|
} else {
|
|
__m256i filter, pw8, src_next_reg;
|
|
|
|
y_offset <<= 5;
|
|
filter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + y_offset));
|
|
pw8 = _mm256_set1_epi16(8);
|
|
for (i = 0; i < height ; i++) {
|
|
LOAD_SRC_DST
|
|
MERGE_NEXT_SRC(src_reg, src_stride)
|
|
FILTER_SRC(filter)
|
|
src_reg = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
sec_reg = _mm256_loadu_si256((__m256i const *) (sec));
|
|
src_reg = _mm256_avg_epu8(src_reg, sec_reg);
|
|
sec+= sec_stride;
|
|
MERGE_WITH_SRC(src_reg, zero_reg)
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
src+= src_stride;
|
|
dst+= dst_stride;
|
|
}
|
|
}
|
|
// x_offset = 8 and y_offset = 0
|
|
} else if (x_offset == 8) {
|
|
if (y_offset == 0) {
|
|
__m256i src_next_reg;
|
|
for (i = 0; i < height ; i++) {
|
|
LOAD_SRC_DST
|
|
AVG_NEXT_SRC(src_reg, 1)
|
|
sec_reg = _mm256_loadu_si256((__m256i const *) (sec));
|
|
src_reg = _mm256_avg_epu8(src_reg, sec_reg);
|
|
sec+= sec_stride;
|
|
// expand each byte to 2 bytes
|
|
MERGE_WITH_SRC(src_reg, zero_reg)
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
src+= src_stride;
|
|
dst+= dst_stride;
|
|
}
|
|
// x_offset = 8 and y_offset = 8
|
|
} else if (y_offset == 8) {
|
|
__m256i src_next_reg, src_avg;
|
|
// load source and another source starting from the next
|
|
// following byte
|
|
src_reg = _mm256_loadu_si256((__m256i const *) (src));
|
|
AVG_NEXT_SRC(src_reg, 1)
|
|
for (i = 0; i < height ; i++) {
|
|
// save current source average
|
|
src_avg = src_reg;
|
|
src+= src_stride;
|
|
LOAD_SRC_DST
|
|
AVG_NEXT_SRC(src_reg, 1)
|
|
// average between previous average to current average
|
|
src_avg = _mm256_avg_epu8(src_avg, src_reg);
|
|
sec_reg = _mm256_loadu_si256((__m256i const *) (sec));
|
|
src_avg = _mm256_avg_epu8(src_avg, sec_reg);
|
|
sec+= sec_stride;
|
|
// expand each byte to 2 bytes
|
|
MERGE_WITH_SRC(src_avg, zero_reg)
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
dst+= dst_stride;
|
|
}
|
|
// x_offset = 8 and y_offset = bilin interpolation
|
|
} else {
|
|
__m256i filter, pw8, src_next_reg, src_avg;
|
|
y_offset <<= 5;
|
|
filter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + y_offset));
|
|
pw8 = _mm256_set1_epi16(8);
|
|
// load source and another source starting from the next
|
|
// following byte
|
|
src_reg = _mm256_loadu_si256((__m256i const *) (src));
|
|
AVG_NEXT_SRC(src_reg, 1)
|
|
for (i = 0; i < height ; i++) {
|
|
// save current source average
|
|
src_avg = src_reg;
|
|
src+= src_stride;
|
|
LOAD_SRC_DST
|
|
AVG_NEXT_SRC(src_reg, 1)
|
|
MERGE_WITH_SRC(src_avg, src_reg)
|
|
FILTER_SRC(filter)
|
|
src_avg = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
sec_reg = _mm256_loadu_si256((__m256i const *) (sec));
|
|
src_avg = _mm256_avg_epu8(src_avg, sec_reg);
|
|
// expand each byte to 2 bytes
|
|
MERGE_WITH_SRC(src_avg, zero_reg)
|
|
sec+= sec_stride;
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
dst+= dst_stride;
|
|
}
|
|
}
|
|
// x_offset = bilin interpolation and y_offset = 0
|
|
} else {
|
|
if (y_offset == 0) {
|
|
__m256i filter, pw8, src_next_reg;
|
|
x_offset <<= 5;
|
|
filter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + x_offset));
|
|
pw8 = _mm256_set1_epi16(8);
|
|
for (i = 0; i < height ; i++) {
|
|
LOAD_SRC_DST
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
FILTER_SRC(filter)
|
|
src_reg = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
sec_reg = _mm256_loadu_si256((__m256i const *) (sec));
|
|
src_reg = _mm256_avg_epu8(src_reg, sec_reg);
|
|
MERGE_WITH_SRC(src_reg, zero_reg)
|
|
sec+= sec_stride;
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
src+= src_stride;
|
|
dst+= dst_stride;
|
|
}
|
|
// x_offset = bilin interpolation and y_offset = 8
|
|
} else if (y_offset == 8) {
|
|
__m256i filter, pw8, src_next_reg, src_pack;
|
|
x_offset <<= 5;
|
|
filter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + x_offset));
|
|
pw8 = _mm256_set1_epi16(8);
|
|
src_reg = _mm256_loadu_si256((__m256i const *) (src));
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
FILTER_SRC(filter)
|
|
// convert each 16 bit to 8 bit to each low and high lane source
|
|
src_pack = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
for (i = 0; i < height ; i++) {
|
|
src+= src_stride;
|
|
LOAD_SRC_DST
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
FILTER_SRC(filter)
|
|
src_reg = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
// average between previous pack to the current
|
|
src_pack = _mm256_avg_epu8(src_pack, src_reg);
|
|
sec_reg = _mm256_loadu_si256((__m256i const *) (sec));
|
|
src_pack = _mm256_avg_epu8(src_pack, sec_reg);
|
|
sec+= sec_stride;
|
|
MERGE_WITH_SRC(src_pack, zero_reg)
|
|
src_pack = src_reg;
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
dst+= dst_stride;
|
|
}
|
|
// x_offset = bilin interpolation and y_offset = bilin interpolation
|
|
} else {
|
|
__m256i xfilter, yfilter, pw8, src_next_reg, src_pack;
|
|
x_offset <<= 5;
|
|
xfilter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + x_offset));
|
|
y_offset <<= 5;
|
|
yfilter = _mm256_load_si256((__m256i const *)
|
|
(bilinear_filters_avx2 + y_offset));
|
|
pw8 = _mm256_set1_epi16(8);
|
|
// load source and another source starting from the next
|
|
// following byte
|
|
src_reg = _mm256_loadu_si256((__m256i const *) (src));
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
|
|
FILTER_SRC(xfilter)
|
|
// convert each 16 bit to 8 bit to each low and high lane source
|
|
src_pack = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
for (i = 0; i < height ; i++) {
|
|
src+= src_stride;
|
|
LOAD_SRC_DST
|
|
MERGE_NEXT_SRC(src_reg, 1)
|
|
FILTER_SRC(xfilter)
|
|
src_reg = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
// merge previous pack to current pack source
|
|
MERGE_WITH_SRC(src_pack, src_reg)
|
|
// filter the source
|
|
FILTER_SRC(yfilter)
|
|
src_pack = _mm256_packus_epi16(exp_src_lo, exp_src_hi);
|
|
sec_reg = _mm256_loadu_si256((__m256i const *) (sec));
|
|
src_pack = _mm256_avg_epu8(src_pack, sec_reg);
|
|
MERGE_WITH_SRC(src_pack, zero_reg)
|
|
src_pack = src_reg;
|
|
sec+= sec_stride;
|
|
CALC_SUM_SSE_INSIDE_LOOP
|
|
dst+= dst_stride;
|
|
}
|
|
}
|
|
}
|
|
CALC_SUM_AND_SSE
|
|
return sum;
|
|
}
|