307 lines
19 KiB
C
307 lines
19 KiB
C
/*
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* Copyright (c) 2017 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "./vpx_dsp_rtcd.h"
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#include "vpx/vpx_integer.h"
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#include "vpx_ports/mem.h"
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#include "vpx_ports/asmdefs_mmi.h"
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void vpx_subtract_block_mmi(int rows, int cols, int16_t *diff,
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ptrdiff_t diff_stride, const uint8_t *src,
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ptrdiff_t src_stride, const uint8_t *pred,
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ptrdiff_t pred_stride) {
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double ftmp[13];
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uint32_t tmp[1];
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if (rows == cols) {
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switch (rows) {
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case 4:
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__asm__ volatile(
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"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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#if _MIPS_SIM == _ABIO32
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"ulw %[tmp0], 0x00(%[src]) \n\t"
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"mtc1 %[tmp0], %[ftmp1] \n\t"
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"ulw %[tmp0], 0x00(%[pred]) \n\t"
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"mtc1 %[tmp0], %[ftmp2] \n\t"
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#else
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"gslwlc1 %[ftmp1], 0x03(%[src]) \n\t"
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"gslwrc1 %[ftmp1], 0x00(%[src]) \n\t"
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"gslwlc1 %[ftmp2], 0x03(%[pred]) \n\t"
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"gslwrc1 %[ftmp2], 0x00(%[pred]) \n\t"
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#endif
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MMI_ADDU(%[src], %[src], %[src_stride])
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MMI_ADDU(%[pred], %[pred], %[pred_stride])
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#if _MIPS_SIM == _ABIO32
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"ulw %[tmp0], 0x00(%[src]) \n\t"
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"mtc1 %[tmp0], %[ftmp3] \n\t"
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"ulw %[tmp0], 0x00(%[pred]) \n\t"
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"mtc1 %[tmp0], %[ftmp4] \n\t"
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#else
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"gslwlc1 %[ftmp3], 0x03(%[src]) \n\t"
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"gslwrc1 %[ftmp3], 0x00(%[src]) \n\t"
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"gslwlc1 %[ftmp4], 0x03(%[pred]) \n\t"
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"gslwrc1 %[ftmp4], 0x00(%[pred]) \n\t"
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#endif
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MMI_ADDU(%[src], %[src], %[src_stride])
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MMI_ADDU(%[pred], %[pred], %[pred_stride])
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#if _MIPS_SIM == _ABIO32
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"ulw %[tmp0], 0x00(%[src]) \n\t"
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"mtc1 %[tmp0], %[ftmp5] \n\t"
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"ulw %[tmp0], 0x00(%[pred]) \n\t"
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"mtc1 %[tmp0], %[ftmp6] \n\t"
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#else
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"gslwlc1 %[ftmp5], 0x03(%[src]) \n\t"
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"gslwrc1 %[ftmp5], 0x00(%[src]) \n\t"
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"gslwlc1 %[ftmp6], 0x03(%[pred]) \n\t"
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"gslwrc1 %[ftmp6], 0x00(%[pred]) \n\t"
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#endif
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MMI_ADDU(%[src], %[src], %[src_stride])
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MMI_ADDU(%[pred], %[pred], %[pred_stride])
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#if _MIPS_SIM == _ABIO32
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"ulw %[tmp0], 0x00(%[src]) \n\t"
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"mtc1 %[tmp0], %[ftmp7] \n\t"
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"ulw %[tmp0], 0x00(%[pred]) \n\t"
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"mtc1 %[tmp0], %[ftmp8] \n\t"
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#else
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"gslwlc1 %[ftmp7], 0x03(%[src]) \n\t"
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"gslwrc1 %[ftmp7], 0x00(%[src]) \n\t"
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"gslwlc1 %[ftmp8], 0x03(%[pred]) \n\t"
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"gslwrc1 %[ftmp8], 0x00(%[pred]) \n\t"
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#endif
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"punpcklbh %[ftmp9], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp10], %[ftmp2], %[ftmp0] \n\t"
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"psubh %[ftmp11], %[ftmp9], %[ftmp10] \n\t"
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"gssdlc1 %[ftmp11], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp11], 0x00(%[diff]) \n\t"
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MMI_ADDU(%[diff], %[diff], %[diff_stride])
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"punpcklbh %[ftmp9], %[ftmp3], %[ftmp0] \n\t"
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"punpcklbh %[ftmp10], %[ftmp4], %[ftmp0] \n\t"
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"psubh %[ftmp11], %[ftmp9], %[ftmp10] \n\t"
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"gssdlc1 %[ftmp11], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp11], 0x00(%[diff]) \n\t"
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MMI_ADDU(%[diff], %[diff], %[diff_stride])
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"punpcklbh %[ftmp9], %[ftmp5], %[ftmp0] \n\t"
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"punpcklbh %[ftmp10], %[ftmp6], %[ftmp0] \n\t"
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"psubh %[ftmp11], %[ftmp9], %[ftmp10] \n\t"
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"gssdlc1 %[ftmp11], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp11], 0x00(%[diff]) \n\t"
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MMI_ADDU(%[diff], %[diff], %[diff_stride])
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"punpcklbh %[ftmp9], %[ftmp7], %[ftmp0] \n\t"
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"punpcklbh %[ftmp10], %[ftmp8], %[ftmp0] \n\t"
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"psubh %[ftmp11], %[ftmp9], %[ftmp10] \n\t"
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"gssdlc1 %[ftmp11], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp11], 0x00(%[diff]) \n\t"
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: [ftmp0] "=&f"(ftmp[0]), [ftmp1] "=&f"(ftmp[1]),
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[ftmp2] "=&f"(ftmp[2]), [ftmp3] "=&f"(ftmp[3]),
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[ftmp4] "=&f"(ftmp[4]), [ftmp5] "=&f"(ftmp[5]),
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[ftmp6] "=&f"(ftmp[6]), [ftmp7] "=&f"(ftmp[7]),
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[ftmp8] "=&f"(ftmp[8]), [ftmp9] "=&f"(ftmp[9]),
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[ftmp10] "=&f"(ftmp[10]), [ftmp11] "=&f"(ftmp[11]),
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#if _MIPS_SIM == _ABIO32
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[tmp0] "=&r"(tmp[0]),
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#endif
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[src] "+&r"(src), [pred] "+&r"(pred), [diff] "+&r"(diff)
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: [src_stride] "r"((mips_reg)src_stride),
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[pred_stride] "r"((mips_reg)pred_stride),
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[diff_stride] "r"((mips_reg)(diff_stride * 2))
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: "memory");
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break;
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case 8:
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__asm__ volatile(
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"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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"li %[tmp0], 0x02 \n\t"
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"1: \n\t"
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"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
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"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
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"gsldlc1 %[ftmp2], 0x07(%[pred]) \n\t"
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"gsldrc1 %[ftmp2], 0x00(%[pred]) \n\t"
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MMI_ADDU(%[src], %[src], %[src_stride])
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MMI_ADDU(%[pred], %[pred], %[pred_stride])
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"gsldlc1 %[ftmp3], 0x07(%[src]) \n\t"
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"gsldrc1 %[ftmp3], 0x00(%[src]) \n\t"
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"gsldlc1 %[ftmp4], 0x07(%[pred]) \n\t"
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"gsldrc1 %[ftmp4], 0x00(%[pred]) \n\t"
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MMI_ADDU(%[src], %[src], %[src_stride])
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MMI_ADDU(%[pred], %[pred], %[pred_stride])
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"gsldlc1 %[ftmp5], 0x07(%[src]) \n\t"
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"gsldrc1 %[ftmp5], 0x00(%[src]) \n\t"
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"gsldlc1 %[ftmp6], 0x07(%[pred]) \n\t"
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"gsldrc1 %[ftmp6], 0x00(%[pred]) \n\t"
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MMI_ADDU(%[src], %[src], %[src_stride])
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MMI_ADDU(%[pred], %[pred], %[pred_stride])
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"gsldlc1 %[ftmp7], 0x07(%[src]) \n\t"
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"gsldrc1 %[ftmp7], 0x00(%[src]) \n\t"
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"gsldlc1 %[ftmp8], 0x07(%[pred]) \n\t"
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"gsldrc1 %[ftmp8], 0x00(%[pred]) \n\t"
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MMI_ADDU(%[src], %[src], %[src_stride])
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MMI_ADDU(%[pred], %[pred], %[pred_stride])
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"punpcklbh %[ftmp9], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp10], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp11], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp12], %[ftmp2], %[ftmp0] \n\t"
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"psubsh %[ftmp9], %[ftmp9], %[ftmp11] \n\t"
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"psubsh %[ftmp10], %[ftmp10], %[ftmp12] \n\t"
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"gssdlc1 %[ftmp9], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp9], 0x00(%[diff]) \n\t"
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"gssdlc1 %[ftmp10], 0x0f(%[diff]) \n\t"
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"gssdrc1 %[ftmp10], 0x08(%[diff]) \n\t"
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MMI_ADDU(%[diff], %[diff], %[diff_stride])
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"punpcklbh %[ftmp9], %[ftmp3], %[ftmp0] \n\t"
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"punpckhbh %[ftmp10], %[ftmp3], %[ftmp0] \n\t"
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"punpcklbh %[ftmp11], %[ftmp4], %[ftmp0] \n\t"
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"punpckhbh %[ftmp12], %[ftmp4], %[ftmp0] \n\t"
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"psubsh %[ftmp9], %[ftmp9], %[ftmp11] \n\t"
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"psubsh %[ftmp10], %[ftmp10], %[ftmp12] \n\t"
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"gssdlc1 %[ftmp9], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp9], 0x00(%[diff]) \n\t"
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"gssdlc1 %[ftmp10], 0x0f(%[diff]) \n\t"
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"gssdrc1 %[ftmp10], 0x08(%[diff]) \n\t"
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MMI_ADDU(%[diff], %[diff], %[diff_stride])
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"punpcklbh %[ftmp9], %[ftmp5], %[ftmp0] \n\t"
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"punpckhbh %[ftmp10], %[ftmp5], %[ftmp0] \n\t"
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"punpcklbh %[ftmp11], %[ftmp6], %[ftmp0] \n\t"
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"punpckhbh %[ftmp12], %[ftmp6], %[ftmp0] \n\t"
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"psubsh %[ftmp9], %[ftmp9], %[ftmp11] \n\t"
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"psubsh %[ftmp10], %[ftmp10], %[ftmp12] \n\t"
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"gssdlc1 %[ftmp9], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp9], 0x00(%[diff]) \n\t"
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"gssdlc1 %[ftmp10], 0x0f(%[diff]) \n\t"
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"gssdrc1 %[ftmp10], 0x08(%[diff]) \n\t"
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MMI_ADDU(%[diff], %[diff], %[diff_stride])
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"punpcklbh %[ftmp9], %[ftmp7], %[ftmp0] \n\t"
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"punpckhbh %[ftmp10], %[ftmp7], %[ftmp0] \n\t"
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"punpcklbh %[ftmp11], %[ftmp8], %[ftmp0] \n\t"
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"punpckhbh %[ftmp12], %[ftmp8], %[ftmp0] \n\t"
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"psubsh %[ftmp9], %[ftmp9], %[ftmp11] \n\t"
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"psubsh %[ftmp10], %[ftmp10], %[ftmp12] \n\t"
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"gssdlc1 %[ftmp9], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp9], 0x00(%[diff]) \n\t"
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"gssdlc1 %[ftmp10], 0x0f(%[diff]) \n\t"
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"gssdrc1 %[ftmp10], 0x08(%[diff]) \n\t"
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MMI_ADDU(%[diff], %[diff], %[diff_stride])
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"addiu %[tmp0], %[tmp0], -0x01 \n\t"
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"bnez %[tmp0], 1b \n\t"
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: [ftmp0] "=&f"(ftmp[0]), [ftmp1] "=&f"(ftmp[1]),
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[ftmp2] "=&f"(ftmp[2]), [ftmp3] "=&f"(ftmp[3]),
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[ftmp4] "=&f"(ftmp[4]), [ftmp5] "=&f"(ftmp[5]),
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[ftmp6] "=&f"(ftmp[6]), [ftmp7] "=&f"(ftmp[7]),
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[ftmp8] "=&f"(ftmp[8]), [ftmp9] "=&f"(ftmp[9]),
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[ftmp10] "=&f"(ftmp[10]), [ftmp11] "=&f"(ftmp[11]),
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[ftmp12] "=&f"(ftmp[12]), [tmp0] "=&r"(tmp[0]), [src] "+&r"(src),
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[pred] "+&r"(pred), [diff] "+&r"(diff)
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: [pred_stride] "r"((mips_reg)pred_stride),
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[src_stride] "r"((mips_reg)src_stride),
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[diff_stride] "r"((mips_reg)(diff_stride * 2))
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: "memory");
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break;
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case 16:
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__asm__ volatile(
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"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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"li %[tmp0], 0x08 \n\t"
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"1: \n\t"
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"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
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"gsldrc1 %[ftmp1], 0x00(%[src]) \n\t"
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"gsldlc1 %[ftmp2], 0x07(%[pred]) \n\t"
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"gsldrc1 %[ftmp2], 0x00(%[pred]) \n\t"
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"gsldlc1 %[ftmp3], 0x0f(%[src]) \n\t"
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"gsldrc1 %[ftmp3], 0x08(%[src]) \n\t"
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"gsldlc1 %[ftmp4], 0x0f(%[pred]) \n\t"
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"gsldrc1 %[ftmp4], 0x08(%[pred]) \n\t"
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MMI_ADDU(%[src], %[src], %[src_stride])
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MMI_ADDU(%[pred], %[pred], %[pred_stride])
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"gsldlc1 %[ftmp5], 0x07(%[src]) \n\t"
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"gsldrc1 %[ftmp5], 0x00(%[src]) \n\t"
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"gsldlc1 %[ftmp6], 0x07(%[pred]) \n\t"
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"gsldrc1 %[ftmp6], 0x00(%[pred]) \n\t"
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"gsldlc1 %[ftmp7], 0x0f(%[src]) \n\t"
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"gsldrc1 %[ftmp7], 0x08(%[src]) \n\t"
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"gsldlc1 %[ftmp8], 0x0f(%[pred]) \n\t"
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"gsldrc1 %[ftmp8], 0x08(%[pred]) \n\t"
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MMI_ADDU(%[src], %[src], %[src_stride])
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MMI_ADDU(%[pred], %[pred], %[pred_stride])
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"punpcklbh %[ftmp9], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp10], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp11], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp12], %[ftmp2], %[ftmp0] \n\t"
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"psubsh %[ftmp9], %[ftmp9], %[ftmp11] \n\t"
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"psubsh %[ftmp10], %[ftmp10], %[ftmp12] \n\t"
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"gssdlc1 %[ftmp9], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp9], 0x00(%[diff]) \n\t"
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"gssdlc1 %[ftmp10], 0x0f(%[diff]) \n\t"
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"gssdrc1 %[ftmp10], 0x08(%[diff]) \n\t"
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"punpcklbh %[ftmp9], %[ftmp3], %[ftmp0] \n\t"
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"punpckhbh %[ftmp10], %[ftmp3], %[ftmp0] \n\t"
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"punpcklbh %[ftmp11], %[ftmp4], %[ftmp0] \n\t"
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"punpckhbh %[ftmp12], %[ftmp4], %[ftmp0] \n\t"
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"psubsh %[ftmp9], %[ftmp9], %[ftmp11] \n\t"
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"psubsh %[ftmp10], %[ftmp10], %[ftmp12] \n\t"
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"gssdlc1 %[ftmp9], 0x17(%[diff]) \n\t"
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"gssdrc1 %[ftmp9], 0x10(%[diff]) \n\t"
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"gssdlc1 %[ftmp10], 0x1f(%[diff]) \n\t"
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"gssdrc1 %[ftmp10], 0x18(%[diff]) \n\t"
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MMI_ADDU(%[diff], %[diff], %[diff_stride])
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"punpcklbh %[ftmp9], %[ftmp5], %[ftmp0] \n\t"
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"punpckhbh %[ftmp10], %[ftmp5], %[ftmp0] \n\t"
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"punpcklbh %[ftmp11], %[ftmp6], %[ftmp0] \n\t"
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"punpckhbh %[ftmp12], %[ftmp6], %[ftmp0] \n\t"
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"psubsh %[ftmp9], %[ftmp9], %[ftmp11] \n\t"
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"psubsh %[ftmp10], %[ftmp10], %[ftmp12] \n\t"
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"gssdlc1 %[ftmp9], 0x07(%[diff]) \n\t"
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"gssdrc1 %[ftmp9], 0x00(%[diff]) \n\t"
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"gssdlc1 %[ftmp10], 0x0f(%[diff]) \n\t"
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"gssdrc1 %[ftmp10], 0x08(%[diff]) \n\t"
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"punpcklbh %[ftmp9], %[ftmp7], %[ftmp0] \n\t"
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"punpckhbh %[ftmp10], %[ftmp7], %[ftmp0] \n\t"
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"punpcklbh %[ftmp11], %[ftmp8], %[ftmp0] \n\t"
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"punpckhbh %[ftmp12], %[ftmp8], %[ftmp0] \n\t"
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"psubsh %[ftmp9], %[ftmp9], %[ftmp11] \n\t"
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"psubsh %[ftmp10], %[ftmp10], %[ftmp12] \n\t"
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"gssdlc1 %[ftmp9], 0x17(%[diff]) \n\t"
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"gssdrc1 %[ftmp9], 0x10(%[diff]) \n\t"
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"gssdlc1 %[ftmp10], 0x1f(%[diff]) \n\t"
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"gssdrc1 %[ftmp10], 0x18(%[diff]) \n\t"
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MMI_ADDU(%[diff], %[diff], %[diff_stride])
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"addiu %[tmp0], %[tmp0], -0x01 \n\t"
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"bnez %[tmp0], 1b \n\t"
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: [ftmp0] "=&f"(ftmp[0]), [ftmp1] "=&f"(ftmp[1]),
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[ftmp2] "=&f"(ftmp[2]), [ftmp3] "=&f"(ftmp[3]),
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[ftmp4] "=&f"(ftmp[4]), [ftmp5] "=&f"(ftmp[5]),
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[ftmp6] "=&f"(ftmp[6]), [ftmp7] "=&f"(ftmp[7]),
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[ftmp8] "=&f"(ftmp[8]), [ftmp9] "=&f"(ftmp[9]),
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[ftmp10] "=&f"(ftmp[10]), [ftmp11] "=&f"(ftmp[11]),
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[ftmp12] "=&f"(ftmp[12]), [tmp0] "=&r"(tmp[0]), [src] "+&r"(src),
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[pred] "+&r"(pred), [diff] "+&r"(diff)
|
|
: [pred_stride] "r"((mips_reg)pred_stride),
|
|
[src_stride] "r"((mips_reg)src_stride),
|
|
[diff_stride] "r"((mips_reg)(diff_stride * 2))
|
|
: "memory");
|
|
break;
|
|
case 32:
|
|
vpx_subtract_block_c(rows, cols, diff, diff_stride, src, src_stride,
|
|
pred, pred_stride);
|
|
break;
|
|
case 64:
|
|
vpx_subtract_block_c(rows, cols, diff, diff_stride, src, src_stride,
|
|
pred, pred_stride);
|
|
break;
|
|
default:
|
|
vpx_subtract_block_c(rows, cols, diff, diff_stride, src, src_stride,
|
|
pred, pred_stride);
|
|
break;
|
|
}
|
|
} else {
|
|
vpx_subtract_block_c(rows, cols, diff, diff_stride, src, src_stride, pred,
|
|
pred_stride);
|
|
}
|
|
}
|