261 lines
6.5 KiB
C
261 lines
6.5 KiB
C
/*
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* Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#ifndef VPX_PORTS_X86_H
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#define VPX_PORTS_X86_H
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#include <stdlib.h>
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#include "vpx_config.h"
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typedef enum {
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VPX_CPU_UNKNOWN = -1,
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VPX_CPU_AMD,
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VPX_CPU_AMD_OLD,
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VPX_CPU_CENTAUR,
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VPX_CPU_CYRIX,
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VPX_CPU_INTEL,
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VPX_CPU_NEXGEN,
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VPX_CPU_NSC,
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VPX_CPU_RISE,
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VPX_CPU_SIS,
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VPX_CPU_TRANSMETA,
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VPX_CPU_TRANSMETA_OLD,
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VPX_CPU_UMC,
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VPX_CPU_VIA,
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VPX_CPU_LAST
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} vpx_cpu_t;
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#if defined(__GNUC__) && __GNUC__ || defined(__ANDROID__)
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#if ARCH_X86_64
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#define cpuid(func, func2, ax, bx, cx, dx)\
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__asm__ __volatile__ (\
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"cpuid \n\t" \
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: "=a" (ax), "=b" (bx), "=c" (cx), "=d" (dx) \
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: "a" (func), "c" (func2));
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#else
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#define cpuid(func, func2, ax, bx, cx, dx)\
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__asm__ __volatile__ (\
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"mov %%ebx, %%edi \n\t" \
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"cpuid \n\t" \
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"xchg %%edi, %%ebx \n\t" \
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: "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
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: "a" (func), "c" (func2));
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#endif
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#elif defined(__SUNPRO_C) || defined(__SUNPRO_CC) /* end __GNUC__ or __ANDROID__*/
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#if ARCH_X86_64
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#define cpuid(func, func2, ax, bx, cx, dx)\
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asm volatile (\
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"xchg %rsi, %rbx \n\t" \
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"cpuid \n\t" \
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"movl %ebx, %edi \n\t" \
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"xchg %rsi, %rbx \n\t" \
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: "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
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: "a" (func), "c" (func2));
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#else
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#define cpuid(func, func2, ax, bx, cx, dx)\
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asm volatile (\
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"pushl %ebx \n\t" \
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"cpuid \n\t" \
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"movl %ebx, %edi \n\t" \
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"popl %ebx \n\t" \
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: "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
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: "a" (func), "c" (func2));
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#endif
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#else /* end __SUNPRO__ */
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#if ARCH_X86_64
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#if defined(_MSC_VER) && _MSC_VER > 1500
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void __cpuidex(int CPUInfo[4], int info_type, int ecxvalue);
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#pragma intrinsic(__cpuidex)
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#define cpuid(func, func2, a, b, c, d) do {\
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int regs[4];\
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__cpuidex(regs, func, func2); \
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a = regs[0]; b = regs[1]; c = regs[2]; d = regs[3];\
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} while(0)
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#else
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void __cpuid(int CPUInfo[4], int info_type);
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#pragma intrinsic(__cpuid)
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#define cpuid(func, func2, a, b, c, d) do {\
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int regs[4];\
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__cpuid(regs, func); \
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a = regs[0]; b = regs[1]; c = regs[2]; d = regs[3];\
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} while (0)
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#endif
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#else
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#define cpuid(func, func2, a, b, c, d)\
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__asm mov eax, func\
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__asm mov ecx, func2\
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__asm cpuid\
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__asm mov a, eax\
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__asm mov b, ebx\
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__asm mov c, ecx\
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__asm mov d, edx
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#endif
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#endif /* end others */
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#define HAS_MMX 0x01
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#define HAS_SSE 0x02
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#define HAS_SSE2 0x04
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#define HAS_SSE3 0x08
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#define HAS_SSSE3 0x10
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#define HAS_SSE4_1 0x20
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#define HAS_AVX 0x40
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#define HAS_AVX2 0x80
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#ifndef BIT
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#define BIT(n) (1<<n)
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#endif
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static int
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x86_simd_caps(void) {
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unsigned int flags = 0;
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unsigned int mask = ~0;
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unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
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char *env;
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(void)reg_ebx;
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/* See if the CPU capabilities are being overridden by the environment */
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env = getenv("VPX_SIMD_CAPS");
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if (env && *env)
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return (int)strtol(env, NULL, 0);
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env = getenv("VPX_SIMD_CAPS_MASK");
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if (env && *env)
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mask = strtol(env, NULL, 0);
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/* Ensure that the CPUID instruction supports extended features */
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cpuid(0, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
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if (reg_eax < 1)
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return 0;
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/* Get the standard feature flags */
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cpuid(1, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
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if (reg_edx & BIT(23)) flags |= HAS_MMX;
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if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
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if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
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if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
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if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
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if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
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if (reg_ecx & BIT(28)) flags |= HAS_AVX;
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/* Get the leaf 7 feature flags. Needed to check for AVX2 support */
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reg_eax = 7;
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reg_ecx = 0;
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cpuid(7, 0, reg_eax, reg_ebx, reg_ecx, reg_edx);
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if (reg_ebx & BIT(5)) flags |= HAS_AVX2;
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return flags & mask;
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}
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vpx_cpu_t vpx_x86_vendor(void);
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#if ARCH_X86_64 && defined(_MSC_VER)
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unsigned __int64 __rdtsc(void);
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#pragma intrinsic(__rdtsc)
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#endif
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static unsigned int
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x86_readtsc(void) {
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#if defined(__GNUC__) && __GNUC__
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unsigned int tsc;
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__asm__ __volatile__("rdtsc\n\t":"=a"(tsc):);
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return tsc;
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#elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
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unsigned int tsc;
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asm volatile("rdtsc\n\t":"=a"(tsc):);
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return tsc;
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#else
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#if ARCH_X86_64
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return (unsigned int)__rdtsc();
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#else
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__asm rdtsc;
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#endif
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#endif
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}
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#if defined(__GNUC__) && __GNUC__
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#define x86_pause_hint()\
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__asm__ __volatile__ ("pause \n\t")
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#elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
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#define x86_pause_hint()\
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asm volatile ("pause \n\t")
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#else
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#if ARCH_X86_64
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#define x86_pause_hint()\
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_mm_pause();
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#else
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#define x86_pause_hint()\
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__asm pause
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#endif
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#endif
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#if defined(__GNUC__) && __GNUC__
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static void
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x87_set_control_word(unsigned short mode) {
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__asm__ __volatile__("fldcw %0" : : "m"(*&mode));
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}
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static unsigned short
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x87_get_control_word(void) {
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unsigned short mode;
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__asm__ __volatile__("fstcw %0\n\t":"=m"(*&mode):);
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return mode;
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}
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#elif defined(__SUNPRO_C) || defined(__SUNPRO_CC)
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static void
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x87_set_control_word(unsigned short mode) {
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asm volatile("fldcw %0" : : "m"(*&mode));
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}
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static unsigned short
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x87_get_control_word(void) {
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unsigned short mode;
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asm volatile("fstcw %0\n\t":"=m"(*&mode):);
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return mode;
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}
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#elif ARCH_X86_64
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/* No fldcw intrinsics on Windows x64, punt to external asm */
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extern void vpx_winx64_fldcw(unsigned short mode);
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extern unsigned short vpx_winx64_fstcw(void);
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#define x87_set_control_word vpx_winx64_fldcw
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#define x87_get_control_word vpx_winx64_fstcw
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#else
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static void
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x87_set_control_word(unsigned short mode) {
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__asm { fldcw mode }
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}
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static unsigned short
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x87_get_control_word(void) {
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unsigned short mode;
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__asm { fstcw mode }
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return mode;
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}
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#endif
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static unsigned short
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x87_set_double_precision(void) {
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unsigned short mode = x87_get_control_word();
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x87_set_control_word((mode&~0x300) | 0x200);
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return mode;
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}
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extern void vpx_reset_mmx_state(void);
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#endif
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