7ad8dbe417
This function was part of an optimization used in VP8 that required caching two macroblocks. This is unused in VP9, and might not survive refactoring to support superblocks, so removing it for now. Change-Id: I744e585206ccc1ef9a402665c33863fc9fb46f0d
183 lines
5.9 KiB
NASM
183 lines
5.9 KiB
NASM
;
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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%include "third_party/x86inc/x86inc.asm"
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SECTION .text
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; unsigned int vp9_sad64x64_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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INIT_XMM sse2
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cglobal sad64x64, 4, 5, 5, src, src_stride, ref, ref_stride, n_rows
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movsxdifnidn src_strideq, src_strided
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movsxdifnidn ref_strideq, ref_strided
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mov n_rowsd, 64
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pxor m0, m0
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.loop:
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movu m1, [refq]
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movu m2, [refq+16]
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movu m3, [refq+32]
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movu m4, [refq+48]
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psadbw m1, [srcq]
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psadbw m2, [srcq+16]
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psadbw m3, [srcq+32]
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psadbw m4, [srcq+48]
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paddd m1, m2
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paddd m3, m4
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add refq, ref_strideq
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paddd m0, m1
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add srcq, src_strideq
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paddd m0, m3
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dec n_rowsd
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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; unsigned int vp9_sad32x32_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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INIT_XMM sse2
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cglobal sad32x32, 4, 5, 5, src, src_stride, ref, ref_stride, n_rows
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movsxdifnidn src_strideq, src_strided
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movsxdifnidn ref_strideq, ref_strided
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mov n_rowsd, 16
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pxor m0, m0
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.loop:
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movu m1, [refq]
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movu m2, [refq+16]
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movu m3, [refq+ref_strideq]
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movu m4, [refq+ref_strideq+16]
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psadbw m1, [srcq]
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psadbw m2, [srcq+16]
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psadbw m3, [srcq+src_strideq]
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psadbw m4, [srcq+src_strideq+16]
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paddd m1, m2
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paddd m3, m4
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lea refq, [refq+ref_strideq*2]
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paddd m0, m1
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lea srcq, [srcq+src_strideq*2]
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paddd m0, m3
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dec n_rowsd
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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; unsigned int vp9_sad16x{8,16}_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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%macro SAD16XN 1
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cglobal sad16x%1, 4, 7, 5, src, src_stride, ref, ref_stride, \
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src_stride3, ref_stride3, n_rows
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movsxdifnidn src_strideq, src_strided
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movsxdifnidn ref_strideq, ref_strided
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lea src_stride3q, [src_strideq*3]
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lea ref_stride3q, [ref_strideq*3]
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mov n_rowsd, %1/4
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pxor m0, m0
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.loop:
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movu m1, [refq]
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movu m2, [refq+ref_strideq]
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movu m3, [refq+ref_strideq*2]
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movu m4, [refq+ref_stride3q]
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psadbw m1, [srcq]
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psadbw m2, [srcq+src_strideq]
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psadbw m3, [srcq+src_strideq*2]
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psadbw m4, [srcq+src_stride3q]
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paddd m1, m2
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paddd m3, m4
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lea refq, [refq+ref_strideq*4]
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paddd m0, m1
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lea srcq, [srcq+src_strideq*4]
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paddd m0, m3
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dec n_rowsd
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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%endmacro
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INIT_XMM sse2
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SAD16XN 16 ; sad16x16_sse2
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SAD16XN 8 ; sad16x8_sse2
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; unsigned int vp9_sad8x{8,16}_sse2(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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%macro SAD8XN 1
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cglobal sad8x%1, 4, 7, 5, src, src_stride, ref, ref_stride, \
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src_stride3, ref_stride3, n_rows
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movsxdifnidn src_strideq, src_strided
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movsxdifnidn ref_strideq, ref_strided
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lea src_stride3q, [src_strideq*3]
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lea ref_stride3q, [ref_strideq*3]
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mov n_rowsd, %1/4
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pxor m0, m0
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.loop:
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movh m1, [refq]
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movhps m1, [refq+ref_strideq]
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movh m2, [refq+ref_strideq*2]
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movhps m2, [refq+ref_stride3q]
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movh m3, [srcq]
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movhps m3, [srcq+src_strideq]
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movh m4, [srcq+src_strideq*2]
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movhps m4, [srcq+src_stride3q]
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psadbw m1, m3
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psadbw m2, m4
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lea refq, [refq+ref_strideq*4]
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paddd m0, m1
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lea srcq, [srcq+src_strideq*4]
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paddd m0, m2
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dec n_rowsd
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jg .loop
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movhlps m1, m0
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paddd m0, m1
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movd eax, m0
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RET
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%endmacro
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INIT_XMM sse2
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SAD8XN 16 ; sad8x16_sse2
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SAD8XN 8 ; sad8x8_sse2
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; unsigned int vp9_sad4x4_sse(uint8_t *src, int src_stride,
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; uint8_t *ref, int ref_stride);
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INIT_MMX sse
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cglobal sad4x4, 4, 4, 8, src, src_stride, ref, ref_stride
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movsxdifnidn src_strideq, src_strided
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movsxdifnidn ref_strideq, ref_strided
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movd m0, [refq]
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movd m1, [refq+ref_strideq]
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movd m2, [srcq]
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movd m3, [srcq+src_strideq]
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lea refq, [refq+ref_strideq*2]
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lea srcq, [srcq+src_strideq*2]
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movd m4, [refq]
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movd m5, [refq+ref_strideq]
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movd m6, [srcq]
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movd m7, [srcq+src_strideq]
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punpckldq m0, m1
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punpckldq m2, m3
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punpckldq m4, m5
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punpckldq m6, m7
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psadbw m0, m2
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psadbw m4, m6
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paddd m0, m4
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movd eax, m0
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RET
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