9a780fa7db
This commit reworks the SSSE3 implementation of the forward 8x8 2D-DCT. It uses a cyclic rotation approach to the temporary xmm registers. It reduces the average cycles from 158 to 154. The SSE2 version uses 169 cycles. Change-Id: I1b79b9642aae0ed3fb3cefb5b70246e6de5d5caa
362 lines
6.8 KiB
NASM
362 lines
6.8 KiB
NASM
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; Copyright (c) 2015 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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%include "third_party/x86inc/x86inc.asm"
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SECTION_RODATA
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pw_11585x2: times 8 dw 23170
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pd_8192: times 4 dd 8192
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%macro TRANSFORM_COEFFS 2
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pw_%1_%2: dw %1, %2, %1, %2, %1, %2, %1, %2
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pw_%2_m%1: dw %2, -%1, %2, -%1, %2, -%1, %2, -%1
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%endmacro
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TRANSFORM_COEFFS 11585, 11585
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TRANSFORM_COEFFS 15137, 6270
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TRANSFORM_COEFFS 16069, 3196
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TRANSFORM_COEFFS 9102, 13623
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SECTION .text
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%if ARCH_X86_64
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INIT_XMM ssse3
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cglobal fdct8x8, 3, 5, 13, input, output, stride
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mova m8, [pd_8192]
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mova m12, [pw_11585x2]
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lea r3, [2 * strideq]
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lea r4, [4 * strideq]
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mova m0, [inputq]
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mova m1, [inputq + r3]
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lea inputq, [inputq + r4]
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mova m2, [inputq]
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mova m3, [inputq + r3]
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lea inputq, [inputq + r4]
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mova m4, [inputq]
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mova m5, [inputq + r3]
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lea inputq, [inputq + r4]
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mova m6, [inputq]
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mova m7, [inputq + r3]
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; left shift by 2 to increase forward transformation precision
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psllw m0, 2
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psllw m1, 2
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psllw m2, 2
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psllw m3, 2
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psllw m4, 2
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psllw m5, 2
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psllw m6, 2
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psllw m7, 2
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; column transform
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; stage 1
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paddw m10, m0, m7
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psubw m0, m7
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paddw m9, m1, m6
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psubw m1, m6
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paddw m7, m2, m5
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psubw m2, m5
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paddw m6, m3, m4
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psubw m3, m4
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; stage 2
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paddw m5, m9, m7
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psubw m9, m7
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paddw m4, m10, m6
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psubw m10, m6
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paddw m7, m1, m2
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psubw m1, m2
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; stage 3
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paddw m6, m4, m5
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psubw m4, m5
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pmulhrsw m1, m12
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pmulhrsw m7, m12
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; sin(pi / 8), cos(pi / 8)
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punpcklwd m2, m10, m9
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punpckhwd m10, m9
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pmaddwd m5, m2, [pw_15137_6270]
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pmaddwd m2, [pw_6270_m15137]
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pmaddwd m9, m10, [pw_15137_6270]
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pmaddwd m10, [pw_6270_m15137]
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paddd m5, m8
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paddd m2, m8
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paddd m9, m8
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paddd m10, m8
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psrad m5, 14
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psrad m2, 14
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psrad m9, 14
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psrad m10, 14
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packssdw m5, m9
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packssdw m2, m10
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pmulhrsw m6, m12
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pmulhrsw m4, m12
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paddw m9, m3, m1
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psubw m3, m1
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paddw m10, m0, m7
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psubw m0, m7
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; stage 4
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; sin(pi / 16), cos(pi / 16)
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punpcklwd m1, m10, m9
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punpckhwd m10, m9
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pmaddwd m7, m1, [pw_16069_3196]
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pmaddwd m1, [pw_3196_m16069]
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pmaddwd m9, m10, [pw_16069_3196]
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pmaddwd m10, [pw_3196_m16069]
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paddd m7, m8
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paddd m1, m8
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paddd m9, m8
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paddd m10, m8
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psrad m7, 14
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psrad m1, 14
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psrad m9, 14
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psrad m10, 14
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packssdw m7, m9
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packssdw m1, m10
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; sin(3 * pi / 16), cos(3 * pi / 16)
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punpcklwd m11, m0, m3
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punpckhwd m0, m3
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pmaddwd m9, m11, [pw_9102_13623]
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pmaddwd m11, [pw_13623_m9102]
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pmaddwd m3, m0, [pw_9102_13623]
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pmaddwd m0, [pw_13623_m9102]
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paddd m9, m8
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paddd m11, m8
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paddd m3, m8
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paddd m0, m8
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psrad m9, 14
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psrad m11, 14
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psrad m3, 14
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psrad m0, 14
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packssdw m9, m3
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packssdw m11, m0
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; transpose
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; stage 1
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punpcklwd m0, m6, m7
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punpcklwd m3, m5, m11
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punpckhwd m6, m7
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punpckhwd m5, m11
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punpcklwd m7, m4, m9
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punpcklwd m10, m2, m1
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punpckhwd m4, m9
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punpckhwd m2, m1
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; stage 2
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punpckldq m9, m0, m3
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punpckldq m1, m6, m5
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punpckhdq m0, m3
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punpckhdq m6, m5
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punpckldq m3, m7, m10
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punpckldq m5, m4, m2
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punpckhdq m7, m10
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punpckhdq m4, m2
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; stage 3
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punpcklqdq m10, m9, m3
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punpckhqdq m9, m3
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punpcklqdq m2, m0, m7
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punpckhqdq m0, m7
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punpcklqdq m3, m1, m5
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punpckhqdq m1, m5
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punpcklqdq m7, m6, m4
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punpckhqdq m6, m4
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; row transform
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; stage 1
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paddw m5, m10, m6
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psubw m10, m6
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paddw m4, m9, m7
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psubw m9, m7
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paddw m6, m2, m1
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psubw m2, m1
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paddw m7, m0, m3
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psubw m0, m3
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;stage 2
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paddw m1, m5, m7
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psubw m5, m7
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paddw m3, m4, m6
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psubw m4, m6
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paddw m7, m9, m2
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psubw m9, m2
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; stage 3
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punpcklwd m6, m1, m3
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punpckhwd m1, m3
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pmaddwd m2, m6, [pw_11585_11585]
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pmaddwd m6, [pw_11585_m11585]
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pmaddwd m3, m1, [pw_11585_11585]
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pmaddwd m1, [pw_11585_m11585]
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paddd m2, m8
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paddd m6, m8
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paddd m3, m8
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paddd m1, m8
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psrad m2, 14
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psrad m6, 14
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psrad m3, 14
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psrad m1, 14
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packssdw m2, m3
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packssdw m6, m1
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pmulhrsw m7, m12
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pmulhrsw m9, m12
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punpcklwd m3, m5, m4
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punpckhwd m5, m4
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pmaddwd m1, m3, [pw_15137_6270]
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pmaddwd m3, [pw_6270_m15137]
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pmaddwd m4, m5, [pw_15137_6270]
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pmaddwd m5, [pw_6270_m15137]
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paddd m1, m8
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paddd m3, m8
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paddd m4, m8
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paddd m5, m8
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psrad m1, 14
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psrad m3, 14
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psrad m4, 14
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psrad m5, 14
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packssdw m1, m4
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packssdw m3, m5
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paddw m4, m0, m9
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psubw m0, m9
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paddw m5, m10, m7
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psubw m10, m7
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; stage 4
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punpcklwd m9, m5, m4
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punpckhwd m5, m4
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pmaddwd m7, m9, [pw_16069_3196]
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pmaddwd m9, [pw_3196_m16069]
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pmaddwd m4, m5, [pw_16069_3196]
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pmaddwd m5, [pw_3196_m16069]
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paddd m7, m8
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paddd m9, m8
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paddd m4, m8
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paddd m5, m8
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psrad m7, 14
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psrad m9, 14
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psrad m4, 14
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psrad m5, 14
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packssdw m7, m4
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packssdw m9, m5
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punpcklwd m4, m10, m0
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punpckhwd m10, m0
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pmaddwd m5, m4, [pw_9102_13623]
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pmaddwd m4, [pw_13623_m9102]
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pmaddwd m0, m10, [pw_9102_13623]
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pmaddwd m10, [pw_13623_m9102]
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paddd m5, m8
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paddd m4, m8
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paddd m0, m8
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paddd m10, m8
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psrad m5, 14
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psrad m4, 14
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psrad m0, 14
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psrad m10, 14
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packssdw m5, m0
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packssdw m4, m10
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; transpose
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; stage 1
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punpcklwd m0, m2, m7
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punpcklwd m10, m1, m4
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punpckhwd m2, m7
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punpckhwd m1, m4
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punpcklwd m7, m6, m5
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punpcklwd m4, m3, m9
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punpckhwd m6, m5
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punpckhwd m3, m9
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; stage 2
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punpckldq m5, m0, m10
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punpckldq m9, m2, m1
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punpckhdq m0, m10
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punpckhdq m2, m1
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punpckldq m10, m7, m4
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punpckldq m1, m6, m3
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punpckhdq m7, m4
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punpckhdq m6, m3
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; stage 3
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punpcklqdq m4, m5, m10
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punpckhqdq m5, m10
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punpcklqdq m3, m0, m7
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punpckhqdq m0, m7
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punpcklqdq m10, m9, m1
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punpckhqdq m9, m1
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punpcklqdq m7, m2, m6
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punpckhqdq m2, m6
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psraw m1, m4, 15
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psraw m6, m5, 15
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psraw m8, m3, 15
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psraw m11, m0, 15
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psubw m4, m1
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psubw m5, m6
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psubw m3, m8
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psubw m0, m11
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psraw m4, 1
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psraw m5, 1
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psraw m3, 1
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psraw m0, 1
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psraw m1, m10, 15
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psraw m6, m9, 15
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psraw m8, m7, 15
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psraw m11, m2, 15
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psubw m10, m1
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psubw m9, m6
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psubw m7, m8
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psubw m2, m11
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psraw m10, 1
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psraw m9, 1
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psraw m7, 1
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psraw m2, 1
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mova [outputq + 0], m4
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mova [outputq + 16], m5
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mova [outputq + 32], m3
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mova [outputq + 48], m0
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mova [outputq + 64], m10
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mova [outputq + 80], m9
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mova [outputq + 96], m7
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mova [outputq + 112], m2
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RET
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%endif
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