189 lines
5.4 KiB
NASM
189 lines
5.4 KiB
NASM
;
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; Copyright (c) 2013 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vpx_idct4x4_16_add_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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INCLUDE vpx_dsp/arm/idct_neon.asm.S
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AREA Block, CODE, READONLY ; name this block of code
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;void vpx_idct4x4_16_add_neon(int16_t *input, uint8_t *dest, int stride)
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;
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; r0 int16_t input
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; r1 uint8_t *dest
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; r2 int stride)
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|vpx_idct4x4_16_add_neon| PROC
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; The 2D transform is done with two passes which are actually pretty
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; similar. We first transform the rows. This is done by transposing
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; the inputs, doing an SIMD column transform (the columns are the
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; transposed rows) and then transpose the results (so that it goes back
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; in normal/row positions). Then, we transform the columns by doing
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; another SIMD column transform.
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; So, two passes of a transpose followed by a column transform.
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; load the inputs into q8-q9, d16-d19
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LOAD_TRAN_LOW_TO_S16 d16, d17, d18, d19, r0
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; generate scalar constants
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; cospi_8_64 = 15137
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movw r0, #0x3b21
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; cospi_16_64 = 11585
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movw r3, #0x2d41
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; cospi_24_64 = 6270
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movw r12, #0x187e
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; transpose the input data
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; 00 01 02 03 d16
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; 10 11 12 13 d17
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; 20 21 22 23 d18
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; 30 31 32 33 d19
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vtrn.16 d16, d17
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vtrn.16 d18, d19
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; generate constant vectors
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vdup.16 d20, r0 ; replicate cospi_8_64
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vdup.16 d21, r3 ; replicate cospi_16_64
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; 00 10 02 12 d16
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; 01 11 03 13 d17
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; 20 30 22 32 d18
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; 21 31 23 33 d19
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vtrn.32 q8, q9
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; 00 10 20 30 d16
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; 01 11 21 31 d17
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; 02 12 22 32 d18
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; 03 13 23 33 d19
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vdup.16 d22, r12 ; replicate cospi_24_64
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; do the transform on transposed rows
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; stage 1
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vmull.s16 q15, d17, d22 ; input[1] * cospi_24_64
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vmull.s16 q1, d17, d20 ; input[1] * cospi_8_64
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; (input[0] + input[2]) * cospi_16_64;
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; (input[0] - input[2]) * cospi_16_64;
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vmull.s16 q8, d16, d21
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vmull.s16 q14, d18, d21
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vadd.s32 q13, q8, q14
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vsub.s32 q14, q8, q14
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; input[1] * cospi_24_64 - input[3] * cospi_8_64;
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; input[1] * cospi_8_64 + input[3] * cospi_24_64;
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vmlsl.s16 q15, d19, d20
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vmlal.s16 q1, d19, d22
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; dct_const_round_shift
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vrshrn.s32 d26, q13, #14
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vrshrn.s32 d27, q14, #14
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vrshrn.s32 d29, q15, #14
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vrshrn.s32 d28, q1, #14
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; stage 2
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; output[0] = step[0] + step[3];
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; output[1] = step[1] + step[2];
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; output[3] = step[0] - step[3];
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; output[2] = step[1] - step[2];
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vadd.s16 q8, q13, q14
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vsub.s16 q9, q13, q14
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vswp d18, d19
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; transpose the results
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; 00 01 02 03 d16
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; 10 11 12 13 d17
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; 20 21 22 23 d18
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; 30 31 32 33 d19
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vtrn.16 d16, d17
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vtrn.16 d18, d19
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; 00 10 02 12 d16
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; 01 11 03 13 d17
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; 20 30 22 32 d18
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; 21 31 23 33 d19
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vtrn.32 q8, q9
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; 00 10 20 30 d16
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; 01 11 21 31 d17
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; 02 12 22 32 d18
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; 03 13 23 33 d19
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; do the transform on columns
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; stage 1
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vadd.s16 d23, d16, d18 ; (input[0] + input[2])
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vsub.s16 d24, d16, d18 ; (input[0] - input[2])
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vmull.s16 q15, d17, d22 ; input[1] * cospi_24_64
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vmull.s16 q1, d17, d20 ; input[1] * cospi_8_64
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; (input[0] + input[2]) * cospi_16_64;
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; (input[0] - input[2]) * cospi_16_64;
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vmull.s16 q13, d23, d21
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vmull.s16 q14, d24, d21
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; input[1] * cospi_24_64 - input[3] * cospi_8_64;
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; input[1] * cospi_8_64 + input[3] * cospi_24_64;
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vmlsl.s16 q15, d19, d20
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vmlal.s16 q1, d19, d22
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; dct_const_round_shift
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vrshrn.s32 d26, q13, #14
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vrshrn.s32 d27, q14, #14
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vrshrn.s32 d29, q15, #14
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vrshrn.s32 d28, q1, #14
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; stage 2
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; output[0] = step[0] + step[3];
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; output[1] = step[1] + step[2];
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; output[3] = step[0] - step[3];
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; output[2] = step[1] - step[2];
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vadd.s16 q8, q13, q14
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vsub.s16 q9, q13, q14
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; The results are in two registers, one of them being swapped. This will
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; be taken care of by loading the 'dest' value in a swapped fashion and
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; also storing them in the same swapped fashion.
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; temp_out[0, 1] = d16, d17 = q8
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; temp_out[2, 3] = d19, d18 = q9 swapped
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; ROUND_POWER_OF_TWO(temp_out[j], 4)
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vrshr.s16 q8, q8, #4
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vrshr.s16 q9, q9, #4
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vld1.32 {d26[0]}, [r1], r2
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vld1.32 {d26[1]}, [r1], r2
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vld1.32 {d27[1]}, [r1], r2
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vld1.32 {d27[0]}, [r1] ; no post-increment
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; ROUND_POWER_OF_TWO(temp_out[j], 4) + dest[j * stride + i]
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vaddw.u8 q8, q8, d26
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vaddw.u8 q9, q9, d27
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; clip_pixel
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vqmovun.s16 d26, q8
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vqmovun.s16 d27, q9
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; do the stores in reverse order with negative post-increment, by changing
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; the sign of the stride
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rsb r2, r2, #0
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vst1.32 {d27[0]}, [r1], r2
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vst1.32 {d27[1]}, [r1], r2
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vst1.32 {d26[1]}, [r1], r2
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vst1.32 {d26[0]}, [r1] ; no post-increment
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bx lr
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ENDP ; |vpx_idct4x4_16_add_neon|
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END
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