0134764fa6
If high bit depth configuration is enabled, but encoding in profile 0, the code now falls back on optimized SSE2 assembler to compute the block errors, similar to when high bit depth is not enabled. Change-Id: I471d1494e541de61a4008f852dbc0d548856484f
99 lines
2.2 KiB
NASM
99 lines
2.2 KiB
NASM
;
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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%define private_prefix vp9
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%include "third_party/x86inc/x86inc.asm"
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SECTION .text
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ALIGN 16
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;
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; int64_t vp9_highbd_block_error_8bit(int32_t *coeff, int32_t *dqcoeff,
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; intptr_t block_size, int64_t *ssz)
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;
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INIT_XMM sse2
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cglobal highbd_block_error_8bit, 3, 3, 8, uqc, dqc, size, ssz
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pxor m4, m4 ; sse accumulator
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pxor m6, m6 ; ssz accumulator
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pxor m5, m5 ; dedicated zero register
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lea uqcq, [uqcq+sizeq*4]
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lea dqcq, [dqcq+sizeq*4]
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neg sizeq
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ALIGN 16
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.loop:
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mova m0, [dqcq+sizeq*4]
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packssdw m0, [dqcq+sizeq*4+mmsize]
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mova m2, [uqcq+sizeq*4]
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packssdw m2, [uqcq+sizeq*4+mmsize]
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mova m1, [dqcq+sizeq*4+mmsize*2]
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packssdw m1, [dqcq+sizeq*4+mmsize*3]
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mova m3, [uqcq+sizeq*4+mmsize*2]
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packssdw m3, [uqcq+sizeq*4+mmsize*3]
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add sizeq, mmsize
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; individual errors are max. 15bit+sign, so squares are 30bit, and
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; thus the sum of 2 should fit in a 31bit integer (+ unused sign bit)
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psubw m0, m2
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pmaddwd m2, m2
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pmaddwd m0, m0
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psubw m1, m3
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pmaddwd m3, m3
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pmaddwd m1, m1
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; accumulate in 64bit
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punpckldq m7, m0, m5
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punpckhdq m0, m5
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paddq m4, m7
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punpckldq m7, m2, m5
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punpckhdq m2, m5
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paddq m6, m7
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punpckldq m7, m1, m5
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punpckhdq m1, m5
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paddq m4, m7
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punpckldq m7, m3, m5
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punpckhdq m3, m5
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paddq m6, m7
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paddq m4, m0
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paddq m4, m1
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paddq m6, m2
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paddq m6, m3
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jnz .loop
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; accumulate horizontally and store in return value
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movhlps m5, m4
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movhlps m7, m6
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paddq m4, m5
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paddq m6, m7
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%if ARCH_X86_64
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movq rax, m4
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movq [sszq], m6
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%else
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mov eax, sszm
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pshufd m5, m4, 0x1
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movq [eax], m6
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movd eax, m4
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movd edx, m5
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%endif
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RET
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