2ff01aa1e4
There is only one avx2 implementation. Drop '_intrin' Change-Id: I887a0d27d58567eaad49f749f127eca61313f312
74 lines
2.9 KiB
C
74 lines
2.9 KiB
C
/*
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* Copyright (c) 2014 The WebM project authors. All Rights Reserved.
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*
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* Usee of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <immintrin.h> // AVX2
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#include "./vp9_rtcd.h"
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#include "vpx/vpx_integer.h"
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#include "vpx_dsp/vpx_dsp_common.h"
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#include "vpx_dsp/x86/bitdepth_conversion_avx2.h"
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int64_t vp9_block_error_avx2(const tran_low_t *coeff, const tran_low_t *dqcoeff,
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intptr_t block_size, int64_t *ssz) {
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__m256i sse_reg, ssz_reg, coeff_reg, dqcoeff_reg;
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__m256i exp_dqcoeff_lo, exp_dqcoeff_hi, exp_coeff_lo, exp_coeff_hi;
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__m256i sse_reg_64hi, ssz_reg_64hi;
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__m128i sse_reg128, ssz_reg128;
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int64_t sse;
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int i;
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const __m256i zero_reg = _mm256_set1_epi16(0);
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// init sse and ssz registerd to zero
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sse_reg = _mm256_set1_epi16(0);
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ssz_reg = _mm256_set1_epi16(0);
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for (i = 0; i < block_size; i += 16) {
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// load 32 bytes from coeff and dqcoeff
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coeff_reg = load_tran_low(coeff + i);
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dqcoeff_reg = load_tran_low(dqcoeff + i);
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// dqcoeff - coeff
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dqcoeff_reg = _mm256_sub_epi16(dqcoeff_reg, coeff_reg);
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// madd (dqcoeff - coeff)
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dqcoeff_reg = _mm256_madd_epi16(dqcoeff_reg, dqcoeff_reg);
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// madd coeff
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coeff_reg = _mm256_madd_epi16(coeff_reg, coeff_reg);
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// expand each double word of madd (dqcoeff - coeff) to quad word
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exp_dqcoeff_lo = _mm256_unpacklo_epi32(dqcoeff_reg, zero_reg);
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exp_dqcoeff_hi = _mm256_unpackhi_epi32(dqcoeff_reg, zero_reg);
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// expand each double word of madd (coeff) to quad word
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exp_coeff_lo = _mm256_unpacklo_epi32(coeff_reg, zero_reg);
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exp_coeff_hi = _mm256_unpackhi_epi32(coeff_reg, zero_reg);
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// add each quad word of madd (dqcoeff - coeff) and madd (coeff)
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sse_reg = _mm256_add_epi64(sse_reg, exp_dqcoeff_lo);
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ssz_reg = _mm256_add_epi64(ssz_reg, exp_coeff_lo);
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sse_reg = _mm256_add_epi64(sse_reg, exp_dqcoeff_hi);
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ssz_reg = _mm256_add_epi64(ssz_reg, exp_coeff_hi);
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}
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// save the higher 64 bit of each 128 bit lane
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sse_reg_64hi = _mm256_srli_si256(sse_reg, 8);
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ssz_reg_64hi = _mm256_srli_si256(ssz_reg, 8);
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// add the higher 64 bit to the low 64 bit
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sse_reg = _mm256_add_epi64(sse_reg, sse_reg_64hi);
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ssz_reg = _mm256_add_epi64(ssz_reg, ssz_reg_64hi);
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// add each 64 bit from each of the 128 bit lane of the 256 bit
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sse_reg128 = _mm_add_epi64(_mm256_castsi256_si128(sse_reg),
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_mm256_extractf128_si256(sse_reg, 1));
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ssz_reg128 = _mm_add_epi64(_mm256_castsi256_si128(ssz_reg),
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_mm256_extractf128_si256(ssz_reg, 1));
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// store the results
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_mm_storel_epi64((__m128i *)(&sse), sse_reg128);
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_mm_storel_epi64((__m128i *)(ssz), ssz_reg128);
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return sse;
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}
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