245 lines
10 KiB
C
245 lines
10 KiB
C
/*
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* Copyright (c) 2015 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#ifndef VPX_DSP_MIPS_MACROS_MSA_H_
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#define VPX_DSP_MIPS_MACROS_MSA_H_
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#include <msa.h>
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#include "./vpx_config.h"
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#include "vpx/vpx_integer.h"
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#define LD_B(RTYPE, psrc) *((const RTYPE *)(psrc))
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#define LD_UB(...) LD_B(v16u8, __VA_ARGS__)
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#define LD_SB(...) LD_B(v16i8, __VA_ARGS__)
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#define LD_H(RTYPE, psrc) *((const RTYPE *)(psrc))
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#define LD_UH(...) LD_H(v8u16, __VA_ARGS__)
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#define LD_SH(...) LD_H(v8i16, __VA_ARGS__)
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#if (__mips_isa_rev >= 6)
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#define LW(psrc) ({ \
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const uint8_t *psrc_m = (const uint8_t *)(psrc); \
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uint32_t val_m; \
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\
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__asm__ __volatile__ ( \
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"lw %[val_m], %[psrc_m] \n\t" \
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\
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: [val_m] "=r" (val_m) \
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: [psrc_m] "m" (*psrc_m) \
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); \
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\
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val_m; \
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})
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#else // !(__mips_isa_rev >= 6)
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#define LW(psrc) ({ \
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const uint8_t *psrc_m = (const uint8_t *)(psrc); \
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uint32_t val_m; \
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\
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__asm__ __volatile__ ( \
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"ulw %[val_m], %[psrc_m] \n\t" \
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\
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: [val_m] "=r" (val_m) \
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: [psrc_m] "m" (*psrc_m) \
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); \
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\
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val_m; \
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})
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#endif // (__mips_isa_rev >= 6)
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/* Description : Load 4 words with stride
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Arguments : Inputs - psrc, stride
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Outputs - out0, out1, out2, out3
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Details : Load word in 'out0' from (psrc)
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Load word in 'out1' from (psrc + stride)
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Load word in 'out2' from (psrc + 2 * stride)
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Load word in 'out3' from (psrc + 3 * stride)
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*/
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#define LW4(psrc, stride, out0, out1, out2, out3) { \
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out0 = LW((psrc)); \
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out1 = LW((psrc) + stride); \
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out2 = LW((psrc) + 2 * stride); \
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out3 = LW((psrc) + 3 * stride); \
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}
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/* Description : Load vectors with 16 byte elements with stride
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Arguments : Inputs - psrc, stride
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Load 16 byte elements in 'out0' from (psrc)
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Load 16 byte elements in 'out1' from (psrc + stride)
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*/
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#define LD_B2(RTYPE, psrc, stride, out0, out1) { \
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out0 = LD_B(RTYPE, (psrc)); \
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out1 = LD_B(RTYPE, (psrc) + stride); \
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}
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#define LD_UB2(...) LD_B2(v16u8, __VA_ARGS__)
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#define LD_B4(RTYPE, psrc, stride, out0, out1, out2, out3) { \
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LD_B2(RTYPE, (psrc), stride, out0, out1); \
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LD_B2(RTYPE, (psrc) + 2 * stride , stride, out2, out3); \
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}
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#define LD_UB4(...) LD_B4(v16u8, __VA_ARGS__)
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/* Description : Load vectors with 8 halfword elements with stride
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Arguments : Inputs - psrc, stride
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Outputs - out0, out1
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Details : Load 8 halfword elements in 'out0' from (psrc)
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Load 8 halfword elements in 'out1' from (psrc + stride)
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*/
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#define LD_H2(RTYPE, psrc, stride, out0, out1) { \
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out0 = LD_H(RTYPE, (psrc)); \
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out1 = LD_H(RTYPE, (psrc) + (stride)); \
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}
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#define LD_H4(RTYPE, psrc, stride, out0, out1, out2, out3) { \
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LD_H2(RTYPE, (psrc), stride, out0, out1); \
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LD_H2(RTYPE, (psrc) + 2 * stride, stride, out2, out3); \
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}
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#define LD_SH4(...) LD_H4(v8i16, __VA_ARGS__)
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/* Description : Dot product & addition of halfword vector elements
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Arguments : Inputs - mult0, mult1, cnst0, cnst1
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Signed halfword elements from 'mult0' are multiplied with
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signed halfword elements from 'cnst0' producing a result
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twice the size of input i.e. signed word.
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The multiplication result of adjacent odd-even elements
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are added to the 'out0' vector
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*/
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#define DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) { \
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out0 = (RTYPE)__msa_dpadd_s_w((v4i32)out0, (v8i16)mult0, (v8i16)cnst0); \
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out1 = (RTYPE)__msa_dpadd_s_w((v4i32)out1, (v8i16)mult1, (v8i16)cnst1); \
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}
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#define DPADD_SH2_SW(...) DPADD_SH2(v4i32, __VA_ARGS__)
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/* Description : Dot product & addition of double word vector elements
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Arguments : Inputs - mult0, mult1
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Each signed word element from 'mult0' is multiplied with itself
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producing an intermediate result twice the size of it
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i.e. signed double word
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The multiplication result of adjacent odd-even elements
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are added to the 'out0' vector
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*/
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#define DPADD_SD2(RTYPE, mult0, mult1, out0, out1) { \
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out0 = (RTYPE)__msa_dpadd_s_d((v2i64)out0, (v4i32)mult0, (v4i32)mult0); \
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out1 = (RTYPE)__msa_dpadd_s_d((v2i64)out1, (v4i32)mult1, (v4i32)mult1); \
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}
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#define DPADD_SD2_SD(...) DPADD_SD2(v2i64, __VA_ARGS__)
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/* Description : Horizontal addition of 4 signed word elements of input vector
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Arguments : Input - in (signed word vector)
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Output - sum_m (i32 sum)
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Return Type - signed word (GP)
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Details : 4 signed word elements of 'in' vector are added together and
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the resulting integer sum is returned
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*/
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#define HADD_SW_S32(in) ({ \
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v2i64 res0_m, res1_m; \
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int32_t sum_m; \
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\
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res0_m = __msa_hadd_s_d((v4i32)in, (v4i32)in); \
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res1_m = __msa_splati_d(res0_m, 1); \
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res0_m = res0_m + res1_m; \
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sum_m = __msa_copy_s_w((v4i32)res0_m, 0); \
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sum_m; \
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})
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/* Description : Horizontal subtraction of unsigned byte vector elements
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Arguments : Inputs - in0, in1
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Each unsigned odd byte element from 'in0' is subtracted from
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even unsigned byte element from 'in0' (pairwise) and the
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halfword result is written to 'out0'
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*/
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#define HSUB_UB2(RTYPE, in0, in1, out0, out1) { \
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out0 = (RTYPE)__msa_hsub_u_h((v16u8)in0, (v16u8)in0); \
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out1 = (RTYPE)__msa_hsub_u_h((v16u8)in1, (v16u8)in1); \
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}
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#define HSUB_UB2_SH(...) HSUB_UB2(v8i16, __VA_ARGS__)
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/* Description : Set element n input vector to GPR value
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Arguments : Inputs - in0, in1, in2, in3
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Output - out
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Return Type - as per RTYPE
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Details : Set element 0 in vector 'out' to value specified in 'in0'
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*/
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#define INSERT_W4(RTYPE, in0, in1, in2, in3, out) { \
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out = (RTYPE)__msa_insert_w((v4i32)out, 0, in0); \
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out = (RTYPE)__msa_insert_w((v4i32)out, 1, in1); \
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out = (RTYPE)__msa_insert_w((v4i32)out, 2, in2); \
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out = (RTYPE)__msa_insert_w((v4i32)out, 3, in3); \
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}
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#define INSERT_W4_UB(...) INSERT_W4(v16u8, __VA_ARGS__)
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#define INSERT_W4_SB(...) INSERT_W4(v16i8, __VA_ARGS__)
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/* Description : Interleave both left and right half of input vectors
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Arguments : Inputs - in0, in1
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Right half of byte elements from 'in0' and 'in1' are
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interleaved and written to 'out0'
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*/
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#define ILVRL_B2(RTYPE, in0, in1, out0, out1) { \
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out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \
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out1 = (RTYPE)__msa_ilvl_b((v16i8)in0, (v16i8)in1); \
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}
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#define ILVRL_B2_UB(...) ILVRL_B2(v16u8, __VA_ARGS__)
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#define ILVRL_H2(RTYPE, in0, in1, out0, out1) { \
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out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \
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out1 = (RTYPE)__msa_ilvl_h((v8i16)in0, (v8i16)in1); \
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}
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#define ILVRL_H2_SW(...) ILVRL_H2(v4i32, __VA_ARGS__)
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/* Description : Pack even double word elements of vector pairs
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Arguments : Inputs - in0, in1, in2, in3
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Even double elements of 'in0' are copied to the left half of
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'out0' & even double elements of 'in1' are copied to the right
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half of 'out0'.
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*/
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#define PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1) { \
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out0 = (RTYPE)__msa_pckev_d((v2i64)in0, (v2i64)in1); \
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out1 = (RTYPE)__msa_pckev_d((v2i64)in2, (v2i64)in3); \
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}
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#define PCKEV_D2_UB(...) PCKEV_D2(v16u8, __VA_ARGS__)
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#define PCKEV_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
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out0, out1, out2, out3) { \
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PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1); \
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PCKEV_D2(RTYPE, in4, in5, in6, in7, out2, out3); \
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}
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#define PCKEV_D4_UB(...) PCKEV_D4(v16u8, __VA_ARGS__)
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/* Description : Sign extend halfword elements from input vector and return
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the result in pair of vectors
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Arguments : Input - in (halfword vector)
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Outputs - out0, out1 (sign extended word vectors)
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Return Type - signed word
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Details : Sign bit of halfword elements from input vector 'in' is
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extracted and interleaved right with same vector 'in0' to
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generate 4 signed word elements in 'out0'
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Then interleaved left with same vector 'in0' to
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generate 4 signed word elements in 'out1'
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*/
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#define UNPCK_SH_SW(in, out0, out1) { \
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v8i16 tmp_m; \
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\
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tmp_m = __msa_clti_s_h((v8i16)in, 0); \
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ILVRL_H2_SW(tmp_m, in, out0, out1); \
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}
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#endif /* VPX_DSP_MIPS_MACROS_MSA_H_ */
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