370 lines
10 KiB
C
370 lines
10 KiB
C
/*
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* Copyright (c) 2012 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "vp8_rtcd.h"
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#if HAVE_DSPR2
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#define CROP_WIDTH 256
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/******************************************************************************
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* Notes:
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*
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* This implementation makes use of 16 bit fixed point version of two multiply
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* constants:
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* 1. sqrt(2) * cos (pi/8)
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* 2. sqrt(2) * sin (pi/8)
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* Since the first constant is bigger than 1, to maintain the same 16 bit
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* fixed point precision as the second one, we use a trick of
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* x * a = x + x*(a-1)
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* so
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* x * sqrt(2) * cos (pi/8) = x + x * (sqrt(2) *cos(pi/8)-1).
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****************************************************************************/
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extern unsigned char ff_cropTbl[256 + 2 * CROP_WIDTH];
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static const int cospi8sqrt2minus1 = 20091;
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static const int sinpi8sqrt2 = 35468;
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inline void prefetch_load_short(short *src)
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{
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__asm__ __volatile__ (
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"pref 0, 0(%[src]) \n\t"
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:
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: [src] "r" (src)
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);
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}
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void vp8_short_idct4x4llm_dspr2(short *input, unsigned char *pred_ptr,
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int pred_stride, unsigned char *dst_ptr,
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int dst_stride)
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{
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int r, c;
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int a1, b1, c1, d1;
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short output[16];
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short *ip = input;
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short *op = output;
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int temp1, temp2;
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int shortpitch = 4;
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int c2, d2;
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int temp3, temp4;
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unsigned char *cm = ff_cropTbl + CROP_WIDTH;
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/* prepare data for load */
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prefetch_load_short(ip + 8);
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/* first loop is unrolled */
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a1 = ip[0] + ip[8];
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b1 = ip[0] - ip[8];
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temp1 = (ip[4] * sinpi8sqrt2) >> 16;
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temp2 = ip[12] + ((ip[12] * cospi8sqrt2minus1) >> 16);
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c1 = temp1 - temp2;
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temp1 = ip[4] + ((ip[4] * cospi8sqrt2minus1) >> 16);
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temp2 = (ip[12] * sinpi8sqrt2) >> 16;
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d1 = temp1 + temp2;
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temp3 = (ip[5] * sinpi8sqrt2) >> 16;
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temp4 = ip[13] + ((ip[13] * cospi8sqrt2minus1) >> 16);
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c2 = temp3 - temp4;
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temp3 = ip[5] + ((ip[5] * cospi8sqrt2minus1) >> 16);
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temp4 = (ip[13] * sinpi8sqrt2) >> 16;
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d2 = temp3 + temp4;
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op[0] = a1 + d1;
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op[12] = a1 - d1;
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op[4] = b1 + c1;
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op[8] = b1 - c1;
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a1 = ip[1] + ip[9];
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b1 = ip[1] - ip[9];
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op[1] = a1 + d2;
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op[13] = a1 - d2;
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op[5] = b1 + c2;
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op[9] = b1 - c2;
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a1 = ip[2] + ip[10];
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b1 = ip[2] - ip[10];
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temp1 = (ip[6] * sinpi8sqrt2) >> 16;
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temp2 = ip[14] + ((ip[14] * cospi8sqrt2minus1) >> 16);
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c1 = temp1 - temp2;
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temp1 = ip[6] + ((ip[6] * cospi8sqrt2minus1) >> 16);
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temp2 = (ip[14] * sinpi8sqrt2) >> 16;
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d1 = temp1 + temp2;
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temp3 = (ip[7] * sinpi8sqrt2) >> 16;
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temp4 = ip[15] + ((ip[15] * cospi8sqrt2minus1) >> 16);
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c2 = temp3 - temp4;
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temp3 = ip[7] + ((ip[7] * cospi8sqrt2minus1) >> 16);
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temp4 = (ip[15] * sinpi8sqrt2) >> 16;
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d2 = temp3 + temp4;
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op[2] = a1 + d1;
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op[14] = a1 - d1;
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op[6] = b1 + c1;
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op[10] = b1 - c1;
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a1 = ip[3] + ip[11];
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b1 = ip[3] - ip[11];
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op[3] = a1 + d2;
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op[15] = a1 - d2;
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op[7] = b1 + c2;
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op[11] = b1 - c2;
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ip = output;
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/* prepare data for load */
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prefetch_load_short(ip + shortpitch);
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/* second loop is unrolled */
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a1 = ip[0] + ip[2];
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b1 = ip[0] - ip[2];
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temp1 = (ip[1] * sinpi8sqrt2) >> 16;
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temp2 = ip[3] + ((ip[3] * cospi8sqrt2minus1) >> 16);
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c1 = temp1 - temp2;
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temp1 = ip[1] + ((ip[1] * cospi8sqrt2minus1) >> 16);
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temp2 = (ip[3] * sinpi8sqrt2) >> 16;
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d1 = temp1 + temp2;
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temp3 = (ip[5] * sinpi8sqrt2) >> 16;
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temp4 = ip[7] + ((ip[7] * cospi8sqrt2minus1) >> 16);
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c2 = temp3 - temp4;
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temp3 = ip[5] + ((ip[5] * cospi8sqrt2minus1) >> 16);
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temp4 = (ip[7] * sinpi8sqrt2) >> 16;
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d2 = temp3 + temp4;
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op[0] = (a1 + d1 + 4) >> 3;
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op[3] = (a1 - d1 + 4) >> 3;
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op[1] = (b1 + c1 + 4) >> 3;
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op[2] = (b1 - c1 + 4) >> 3;
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a1 = ip[4] + ip[6];
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b1 = ip[4] - ip[6];
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op[4] = (a1 + d2 + 4) >> 3;
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op[7] = (a1 - d2 + 4) >> 3;
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op[5] = (b1 + c2 + 4) >> 3;
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op[6] = (b1 - c2 + 4) >> 3;
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a1 = ip[8] + ip[10];
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b1 = ip[8] - ip[10];
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temp1 = (ip[9] * sinpi8sqrt2) >> 16;
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temp2 = ip[11] + ((ip[11] * cospi8sqrt2minus1) >> 16);
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c1 = temp1 - temp2;
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temp1 = ip[9] + ((ip[9] * cospi8sqrt2minus1) >> 16);
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temp2 = (ip[11] * sinpi8sqrt2) >> 16;
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d1 = temp1 + temp2;
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temp3 = (ip[13] * sinpi8sqrt2) >> 16;
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temp4 = ip[15] + ((ip[15] * cospi8sqrt2minus1) >> 16);
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c2 = temp3 - temp4;
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temp3 = ip[13] + ((ip[13] * cospi8sqrt2minus1) >> 16);
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temp4 = (ip[15] * sinpi8sqrt2) >> 16;
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d2 = temp3 + temp4;
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op[8] = (a1 + d1 + 4) >> 3;
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op[11] = (a1 - d1 + 4) >> 3;
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op[9] = (b1 + c1 + 4) >> 3;
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op[10] = (b1 - c1 + 4) >> 3;
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a1 = ip[12] + ip[14];
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b1 = ip[12] - ip[14];
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op[12] = (a1 + d2 + 4) >> 3;
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op[15] = (a1 - d2 + 4) >> 3;
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op[13] = (b1 + c2 + 4) >> 3;
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op[14] = (b1 - c2 + 4) >> 3;
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ip = output;
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for (r = 0; r < 4; r++)
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{
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for (c = 0; c < 4; c++)
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{
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short a = ip[c] + pred_ptr[c] ;
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dst_ptr[c] = cm[a] ;
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}
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ip += 4;
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dst_ptr += dst_stride;
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pred_ptr += pred_stride;
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}
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}
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void vp8_dc_only_idct_add_dspr2(short input_dc, unsigned char *pred_ptr, int pred_stride, unsigned char *dst_ptr, int dst_stride)
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{
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int a1;
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int i, absa1;
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int t2, vector_a1, vector_a;
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/* a1 = ((input_dc + 4) >> 3); */
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__asm__ __volatile__ (
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"addi %[a1], %[input_dc], 4 \n\t"
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"sra %[a1], %[a1], 3 \n\t"
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: [a1] "=r" (a1)
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: [input_dc] "r" (input_dc)
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);
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if (a1 < 0)
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{
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/* use quad-byte
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* input and output memory are four byte aligned
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*/
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__asm__ __volatile__ (
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"abs %[absa1], %[a1] \n\t"
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"replv.qb %[vector_a1], %[absa1] \n\t"
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: [absa1] "=r" (absa1), [vector_a1] "=r" (vector_a1)
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: [a1] "r" (a1)
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);
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/* use (a1 - predptr[c]) instead a1 + predptr[c] */
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for (i = 4; i--;)
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{
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__asm__ __volatile__ (
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"lw %[t2], 0(%[pred_ptr]) \n\t"
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"add %[pred_ptr], %[pred_ptr], %[pred_stride] \n\t"
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"subu_s.qb %[vector_a], %[t2], %[vector_a1] \n\t"
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"sw %[vector_a], 0(%[dst_ptr]) \n\t"
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"add %[dst_ptr], %[dst_ptr], %[dst_stride] \n\t"
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: [t2] "=&r" (t2), [vector_a] "=&r" (vector_a),
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[dst_ptr] "+&r" (dst_ptr), [pred_ptr] "+&r" (pred_ptr)
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: [dst_stride] "r" (dst_stride), [pred_stride] "r" (pred_stride), [vector_a1] "r" (vector_a1)
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);
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}
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}
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else
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{
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/* use quad-byte
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* input and output memory are four byte aligned
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*/
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__asm__ __volatile__ (
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"replv.qb %[vector_a1], %[a1] \n\t"
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: [vector_a1] "=r" (vector_a1)
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: [a1] "r" (a1)
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);
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for (i = 4; i--;)
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{
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__asm__ __volatile__ (
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"lw %[t2], 0(%[pred_ptr]) \n\t"
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"add %[pred_ptr], %[pred_ptr], %[pred_stride] \n\t"
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"addu_s.qb %[vector_a], %[vector_a1], %[t2] \n\t"
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"sw %[vector_a], 0(%[dst_ptr]) \n\t"
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"add %[dst_ptr], %[dst_ptr], %[dst_stride] \n\t"
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: [t2] "=&r" (t2), [vector_a] "=&r" (vector_a),
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[dst_ptr] "+&r" (dst_ptr), [pred_ptr] "+&r" (pred_ptr)
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: [dst_stride] "r" (dst_stride), [pred_stride] "r" (pred_stride), [vector_a1] "r" (vector_a1)
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);
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}
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}
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}
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void vp8_short_inv_walsh4x4_dspr2(short *input, short *mb_dqcoeff)
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{
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short output[16];
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int i;
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int a1, b1, c1, d1;
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int a2, b2, c2, d2;
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short *ip = input;
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short *op = output;
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prefetch_load_short(ip);
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for (i = 4; i--;)
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{
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a1 = ip[0] + ip[12];
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b1 = ip[4] + ip[8];
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c1 = ip[4] - ip[8];
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d1 = ip[0] - ip[12];
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op[0] = a1 + b1;
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op[4] = c1 + d1;
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op[8] = a1 - b1;
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op[12] = d1 - c1;
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ip++;
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op++;
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}
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ip = output;
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op = output;
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prefetch_load_short(ip);
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for (i = 4; i--;)
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{
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a1 = ip[0] + ip[3] + 3;
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b1 = ip[1] + ip[2];
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c1 = ip[1] - ip[2];
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d1 = ip[0] - ip[3] + 3;
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a2 = a1 + b1;
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b2 = d1 + c1;
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c2 = a1 - b1;
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d2 = d1 - c1;
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op[0] = a2 >> 3;
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op[1] = b2 >> 3;
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op[2] = c2 >> 3;
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op[3] = d2 >> 3;
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ip += 4;
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op += 4;
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}
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for (i = 0; i < 16; i++)
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{
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mb_dqcoeff[i * 16] = output[i];
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}
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}
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void vp8_short_inv_walsh4x4_1_dspr2(short *input, short *mb_dqcoeff)
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{
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int a1;
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a1 = ((input[0] + 3) >> 3);
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__asm__ __volatile__ (
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"sh %[a1], 0(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 32(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 64(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 96(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 128(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 160(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 192(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 224(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 256(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 288(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 320(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 352(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 384(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 416(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 448(%[mb_dqcoeff]) \n\t"
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"sh %[a1], 480(%[mb_dqcoeff]) \n\t"
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:
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: [a1] "r" (a1), [mb_dqcoeff] "r" (mb_dqcoeff)
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);
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}
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#endif
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