33df6d1fc1
The recent compiler can generate optimized code that uses NEON registers for various operations besides floating-point operations. Therefore, only saving callee-saved registers d8 - d15 at the beginning of the encoder/decoder is not enough anymore. This patch added register saving code in VP8 NEON functions that use those registers. Change-Id: Ie9e44f5188cf410990c8aaaac68faceee9dffd31
82 lines
2.4 KiB
NASM
82 lines
2.4 KiB
NASM
;
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license and patent
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; grant that can be found in the LICENSE file in the root of the source
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; tree. All contributing project authors may be found in the AUTHORS
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; file in the root of the source tree.
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;
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EXPORT |idct_dequant_0_2x_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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;void idct_dequant_0_2x_neon(short *q, short dq,
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; unsigned char *dst, int stride);
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; r0 *q
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; r1 dq
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; r2 *dst
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; r3 stride
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|idct_dequant_0_2x_neon| PROC
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push {r4, r5}
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vpush {d8-d15}
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add r12, r2, #4
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vld1.32 {d2[0]}, [r2], r3
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vld1.32 {d8[0]}, [r12], r3
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vld1.32 {d2[1]}, [r2], r3
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vld1.32 {d8[1]}, [r12], r3
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vld1.32 {d4[0]}, [r2], r3
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vld1.32 {d10[0]}, [r12], r3
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vld1.32 {d4[1]}, [r2], r3
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vld1.32 {d10[1]}, [r12], r3
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ldrh r12, [r0] ; lo q
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ldrh r4, [r0, #32] ; hi q
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mov r5, #0
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strh r5, [r0]
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strh r5, [r0, #32]
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sxth r12, r12 ; lo
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mul r0, r12, r1
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add r0, r0, #4
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asr r0, r0, #3
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vdup.16 q0, r0
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sxth r4, r4 ; hi
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mul r0, r4, r1
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add r0, r0, #4
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asr r0, r0, #3
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vdup.16 q3, r0
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vaddw.u8 q1, q0, d2 ; lo
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vaddw.u8 q2, q0, d4
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vaddw.u8 q4, q3, d8 ; hi
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vaddw.u8 q5, q3, d10
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sub r2, r2, r3, lsl #2 ; dst - 4*stride
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add r0, r2, #4
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vqmovun.s16 d2, q1 ; lo
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vqmovun.s16 d4, q2
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vqmovun.s16 d8, q4 ; hi
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vqmovun.s16 d10, q5
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vst1.32 {d2[0]}, [r2], r3 ; lo
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vst1.32 {d8[0]}, [r0], r3 ; hi
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vst1.32 {d2[1]}, [r2], r3
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vst1.32 {d8[1]}, [r0], r3
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vst1.32 {d4[0]}, [r2], r3
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vst1.32 {d10[0]}, [r0], r3
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vst1.32 {d4[1]}, [r2]
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vst1.32 {d10[1]}, [r0]
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vpop {d8-d15}
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pop {r4, r5}
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bx lr
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ENDP ; |idct_dequant_0_2x_neon|
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END
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