Commit Graph

2723 Commits

Author SHA1 Message Date
JackyChen
65f60f8e8c Merge "SSE2 code for the filter in MFQE." 2015-01-23 11:08:16 -08:00
Yaowu Xu
eda179764f Replace divide with look-up
This commit replaces an integer divide with a table-lookup. It is
to improve decoding speed, and at the same time, to reduce possible
complications with a bug in AMD Family 12h processors:

"665 Integer Divide Instruction May Cause Unpredictable Behavior"

Change-Id: I678b707a538798a923850bac467e66e847e6def7
2015-01-23 09:02:07 -08:00
Johann
a18da9760a Revert "Merge branch 'frame-parallel' to enable frame parallel decode in master branch."
This reverts commit bde04ce503

Change-Id: I053dae04c761b04a36dc239558503905a14d2470
2015-01-23 08:42:02 -08:00
hkuang
bde04ce503 Merge branch 'frame-parallel' to enable frame parallel decode in master branch.
In frame parallel decode, libvpx decoder decodes several frames on all
cpus in parallel fashion. If not being flushed, it will only return frame
when all the cpus are busy. If getting flushed, it will return all the
frames in the decoder. Compare with current serial decode mode in which
libvpx decoder is idle between decode calls, libvpx decoder is busy
between decode calls. VP9 frame parallel decode is >30% faster than serial
decode with tile parallel threading which will makes devices play 1080P
VP9 videos more easily.

* frame-parallel:
  Add error handling for frame parallel decode and unit test for that.
  Fix a bug in frame parallel decode and add a unit test for that.
  Add two test vectors to test frame parallel decode.
  Add key frame seeking to webmdec and webm_video_source.
  Implement frame parallel decode for VP9.
  Increase the thread test range to cover 5, 6, 7, 8 threads.
  Fix a bug in adding frame parallel unit test.
  Add VP9 frame-parallel unit test.
  Manually pick "Make the api behavior conform to api spec." from master branch.
  Move vp9_dec_build_inter_predictors_* to decoder folder.
  Add segmentation map array for current and last frame segmentation.
  Include the right header for VP9 worker thread.
  Move vp9_thread.* to common.
  ctrl_get_reference does not need user_priv.
  Seperate the frame buffers from VP9 encoder/decoder structure.
  Revert "Revert "Revert "Revert 3 patches from Hangyu to get Chrome to build:"""

 Conflicts:
       test/codec_factory.h
       test/decode_test_driver.cc
       test/decode_test_driver.h
       test/invalid_file_test.cc
       test/test-data.sha1
       test/test.mk
       test/test_vectors.cc
       vp8/vp8_dx_iface.c
       vp9/common/vp9_alloccommon.c
       vp9/common/vp9_entropymode.c
       vp9/common/vp9_loopfilter_thread.c
       vp9/common/vp9_loopfilter_thread.h
       vp9/common/vp9_mvref_common.c
       vp9/common/vp9_onyxc_int.h
       vp9/common/vp9_reconinter.c
       vp9/decoder/vp9_decodeframe.c
       vp9/decoder/vp9_decodeframe.h
       vp9/decoder/vp9_decodemv.c
       vp9/decoder/vp9_decoder.c
       vp9/decoder/vp9_decoder.h
       vp9/encoder/vp9_encoder.c
       vp9/encoder/vp9_pickmode.c
       vp9/encoder/vp9_rdopt.c
       vp9/vp9_cx_iface.c
       vp9/vp9_dx_iface.c

Change-Id: Ib92eb35851c172d0624970e312ed515054e5ca64
2015-01-22 18:18:53 -08:00
Frank Galligan
469ff48d7b Merge "Add Neon intrinsics for vp9_avg_8x8_neon" 2015-01-20 14:38:39 -08:00
Yunqing Wang
6d7b7abf52 Add non420 code in multi-threaded loopfilter
Added non420 part back to make it consistent with single
thread code in vp9_loopfilter.c.

Change-Id: I8ca255d73bffebae294d2627d6655eafe535cb90
2015-01-20 09:31:47 -08:00
JackyChen
09673deba9 SSE2 code for the filter in MFQE.
The SSE2 code is from VP8 MFQE, reuse it in VP9. No change on VP8
side. In our testing, we achieve 2X speed by adopting this change.

Change-Id: Ib2b14144ae57c892005c1c4b84e3379d02e56716
2015-01-18 16:07:59 -08:00
Yunqing Wang
e76eaf05b1 vp9_ethread: add parallel loopfilter
1. Added row-based loopfilter in encoder;
2. Moved common multi-threaded loopfilter functions from decoder
   to common;
3. Merged multi-threaded loopfilter code, and made encoder/
   decoder call same function to reduce code duplication.

Encoder tests showed that 1% - 2% speedup was seen for good-quality
2-pass mode(at speed 3); 1% - 3% speedup using 2 threads and 4% - 6%
speedup using 4 threads were seen for real-time mode(at speed 7).

Change-Id: I8a4ac51c2ad9bab9fa7b864e90743931c53ec1c4
2015-01-16 17:19:27 -08:00
Frank Galligan
6e7e1cf32f Add Neon intrinsics for vp9_avg_8x8_neon
On Nexus 7 speed -5, -6, -7, and -8 saw about a 1% increase
in perf for 480p. Speeds -5, -6, -7, and -8 saw about a 1.5%
increase in perf for 720p.

Tested on Nexus 7, built with ndk r10d, gcc 4.9.

Change-Id: Ibf17ebfd952a6aec941719bd8306df8ec4574bee
2015-01-15 15:32:40 -08:00
Yaowu Xu
829a01dbb7 Merge "Add encoder control for setting color space" 2015-01-14 14:14:34 -08:00
Yaowu Xu
e94b415c34 Add encoder control for setting color space
This commit adds encoder side control for vp9 to set color space info
in the output compressed bitstream.

It also amends the "vp9_encoder_params_get_to_decoder" test to verify
the correct color space information is passed from the encoder end to
decoder end.

Change-Id: Ibf5fba2edcb2a8dc37557f6fae5c7816efa52650
2015-01-14 10:17:14 -08:00
Frank Galligan
ec1d8387e1 Add 64x64 sub_pel_variance Neon function
On Nexus 7 speed -5, -6, -7, and -8 saw about a 15% increase
in perf for 480p. Speeds -5, -6, -7, and -8 saw about a 10%
increase in perf for 720p.

Tested on Nexus 7, built with ndk r10d, gcc 4.9.

Change-Id: I2fa5315845e3021c9a6e2ea47e52e68b398d8334
2015-01-14 08:36:24 -08:00
Frank Galligan
74d40cd507 Add 64x variance Neon functions
Add optimized Neon functions of:
vp9_variance32x64
vp9_variance64x32
vp9_variance64x64

On Nexus 7 speed -5 and -6 saw about a 4% increase in perf.
Speeds -7 and -8 saw about a 6% increase in perf.
Tested on Nexus 7, built with ndk r10d, gcc 4.9.

Change-Id: I5a81f13c9897eb927fa39662530f5524a0f768fa
2015-01-13 15:08:13 -08:00
James Zern
4d6838627d Merge "vp9: add per-tile longjmp error handling" 2015-01-08 15:53:37 -08:00
Johann
00bbe342c2 Merge "Disable vp9 _8_ loopfilters" 2015-01-08 12:47:52 -08:00
Yaowu Xu
01eec75858 Merge "Refactor calculation of tile_cols" 2015-01-07 16:24:57 -08:00
JackyChen
1883c940b9 Merge "Use qdiff to adjust the threshold of sad and variance in MFQE." 2015-01-07 14:57:46 -08:00
Yaowu Xu
e9cf9b7dfe Refactor calculation of tile_cols
Change-Id: I2c38ea2bcf6d221a0b6b2fb9be4cebbee21006a3
2015-01-07 14:28:59 -08:00
JackyChen
60cf5cf7b2 Use qdiff to adjust the threshold of sad and variance in MFQE.
When qdiff is larger, the sad/variance threshold should also be
higher which indicates a more aggressive action on MFQE.

Change-Id: I44c5c93572805458d4f87fdc7619cc9d8a522185
2015-01-07 09:07:10 -08:00
Johann
377b6682f9 Disable vp9 _8_ loopfilters
Investigating https://code.google.com/p/chromium/issues/detail?id=443839

Change-Id: Ibb7485d835c5aa5e1d40f31715596ba8d208eedb
2015-01-06 19:26:11 -08:00
Johann
b1ba4cc394 Rearrange loopfilter functions
Separate functions and rename files. This will make it easier to disable
some functions later to help work around a compiler issue in chromium.

Change-Id: I7f30e109f77c4cd22e2eda7bd006672f090c1dc5
2015-01-06 19:26:11 -08:00
Deb Mukherjee
0c2ee67ad6 Merge "Enable coefficient range checking for 10-/12-bit" 2015-01-06 14:59:08 -08:00
Deb Mukherjee
0ce2a27e9b Enable coefficient range checking for 10-/12-bit
Also fixes a broken build with --enable-coefficient-range-checking
configuration option.

Change-Id: Icc536f53088e8cec59dfb8f635668555fdb9125e
2015-01-06 02:40:51 -08:00
JackyChen
fe23539d58 Adopt weighted averaging in MFQE.
By using weighted averaging in the calculation of the frames to be
displayed, we get an average gain of more than 1 db for key frames
whose base qp are 20 higher than non-key frames.

Change-Id: I7bcb2e7b9c6420ea3f73f33204d18b072dffd17c
2015-01-05 11:38:42 -08:00
Jim Bankoski
b3c66f8a2f WIP: Remove giant value cost table
Change-Id: Iabe8a8868a747626c24bb13f1796f4c7827af367
2014-12-23 15:06:17 -08:00
Jingning Han
d0f2377027 Revert "Revert "Removal of legacy zbin_extra / zbin_oq_value.""
This reverts commit 9946ee23e0.

Fix the ssse3 asm function.

Change-Id: I07f77a63aa98087626e45c4e87aa5dcafc0b0b07
2014-12-22 10:09:25 -08:00
James Zern
953dd1894d vp9: add per-tile longjmp error handling
this avoids longjmp'ing from another thread on error which will cause
undesired behavior

Change-Id: Ic9074ed8cc4243944bf2539d6e482f213f4e8c86
2014-12-19 11:50:04 -08:00
Paul Wilkins
9946ee23e0 Revert "Removal of legacy zbin_extra / zbin_oq_value."
This reverts commit e9b586e21b.

Change-Id: I5b36e6727da6c05278d97e2c37b80c109f79bed4
2014-12-19 15:02:58 +00:00
Paul Wilkins
8ac3f9adaa Merge "Removal of legacy zbin_extra / zbin_oq_value." 2014-12-19 03:37:02 -08:00
James Zern
b32ba09d35 Merge "make vp9 encoder static initializers thread safe" 2014-12-18 18:48:30 -08:00
Jim Bankoski
cd60930814 make vp9 encoder static initializers thread safe
Change-Id: If2d0888d13ebe52bc7c3b16f16319408a86ab6de
2014-12-18 15:50:46 -08:00
Paul Wilkins
e9b586e21b Removal of legacy zbin_extra / zbin_oq_value.
zbin extra / zbin_oq_value was widely passed around,
hence removal touches a lot of code.

Change-Id: Idc94359735b60c38a160e4385ae09d5ca8b6b8e5
2014-12-18 16:49:11 +00:00
hkuang
b7166143d0 Let YUV plane share the same dqcoeff buffer.
Remove unnecessary dqcoeff from macroblockd which reduce macroblockd
size by 16384 bytes.

Change-Id: Ia379a703b4fee81c8fd4698b52488a85a90c9bc2
2014-12-17 18:29:07 -08:00
JackyChen
9bc7974552 Merge "Add rectangle block support for MFQE." 2014-12-17 15:10:02 -08:00
JackyChen
021e244a51 Merge "Use bit_depth in VP9Common as the flag of highbit." 2014-12-17 09:30:32 -08:00
Jingning Han
00d2211929 Merge "Remove reset mode_info array per frame" 2014-12-17 09:24:44 -08:00
JackyChen
b363cedcd1 Use bit_depth in VP9Common as the flag of highbit.
Change-Id: I881aefbe68f9c10bb4629a2a5ee1e42a225d5ab7
2014-12-16 21:45:01 -08:00
James Yu
aeeaa67987 VP9 common for ARMv8 by using NEON intrinsics 15
Re-write
- vp9_lpf_horizontal_4_dual_neon
in vp9_loopfilter_16_neon.c

Change-Id: Ie14f63d352f9564ad01db3939a61d91cf6d21a31
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-16 20:00:26 -08:00
Johann
ebc1951c7c Merge "Use defines for inline and __builtin_prefetch" 2014-12-16 18:04:04 -08:00
JackyChen
9931070094 Add rectangle block support for MFQE.
Only for the rectangle blocks larger than 16X16, SAD and Variance are
still based on the internal square blocks.

Change-Id: I3754da1b0254147313f86a0140dbf4f980f06a5a
2014-12-16 16:35:54 -08:00
Johann
4f7060a431 Merge "VP9 common for ARMv8 by using NEON intrinsics 16" 2014-12-16 16:15:48 -08:00
Jingning Han
ccdc448b70 Remove reset mode_info array per frame
The mode_info array was unnecessarily reset to zero every frame
when error resilient mode turned on, given that the mode info
values per block will be assigned during mode search stage.

This commit removes this reset operation. It reduces the runtime
cost on memset operation to 1/3. The overall speed -6 runtime is
reduced by 2%.

Change-Id: I32ecb73338d8995cc0c5147de09357364f13d45b
2014-12-16 15:54:24 -08:00
Johann
2fdbf70d40 Use defines for inline and __builtin_prefetch
These were established for compatibility. Make sure to use them.

Most frequently they manifest as issues on Visual Studio builds.

Change-Id: I39d764d2eb341b999d7a6132cb44b2acfc511160
2014-12-16 15:21:19 -08:00
Frank Galligan
5fdd0f1fe0 Merge "Revert "Revert "Add support for setting byte alignment.""" 2014-12-16 15:14:17 -08:00
James Yu
aa8dd897c1 VP9 common for ARMv8 by using NEON intrinsics 16
Add vp9_reconintra_neon.c
- vp9_v_predictor_4x4_neon
- vp9_v_predictor_8x8_neon
- vp9_v_predictor_16x16_neon
- vp9_v_predictor_32x32_neon
- vp9_h_predictor_4x4_neon
- vp9_h_predictor_8x8_neon
- vp9_h_predictor_16x16_neon
- vp9_h_predictor_32x32_neon
- vp9_tm_predictor_4x4_neon
- vp9_tm_predictor_8x8_neon
- vp9_tm_predictor_16x16_neon
- vp9_tm_predictor_32x32_neon

Change-Id: Ib5d54a4766a1b5127169045659974f33aa98376d
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-16 12:57:52 -08:00
James Yu
ba05a4c640 VP9 common for ARMv8 by using NEON intrinsics 19
Delete vp9_dc_only_idct_add_neon.c

The function was merged with vp9_short_idct4x4_1_add (later
vp9_idct4x4_1_add) in d2de1ca and should have been deleted then.

Change-Id: Ie58ba3dd9dc7330a8f1238dd7dd71c9ed4639b94
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-16 11:14:12 -08:00
JackyChen
e7bad92689 Fixed MFQE crash issue for highbit depth.
Check the flags, no MFQE for highbit now. Will add highbit support
latter.

Change-Id: I548c27593e0f47ab7f4c92b45f14fb037dc86591
2014-12-16 10:07:38 -08:00
Yaowu Xu
b60ae45f36 Merge "Prevent decoder from using uninitialized entropy context." 2014-12-16 09:30:24 -08:00
Jim Bankoski
abc5a66770 Merge "Fix the comments." 2014-12-16 06:25:01 -08:00
Johann
1d059fa23e Merge "VP9 common for ARMv8 by using NEON intrinsics 06" 2014-12-15 14:49:33 -08:00
Johann
37ea1e1218 Merge "VP9 common for ARMv8 by using NEON intrinsics 05" 2014-12-15 14:48:53 -08:00
Frank Galligan
c4f7079ad4 Revert "Revert "Add support for setting byte alignment.""
This reverts commit 91471d6aad.

Fixes the compile issues if post_proc is enabled.

Change-Id: Ib40a15ce2c194f9b5adfa65a17ab01ddf60f5a59
2014-12-15 12:20:37 -08:00
James Yu
4f856cd7fa VP9 common for ARMv8 by using NEON intrinsics 06
Add vp9_iht8x8_add_neon.c
- vp9_iht8x8_64_add_neon

The assembly did not previously implement tx_type 0
BUG=716

Change-Id: Icfc99dd24f3d59047f9184a7d0c761ba7e3de934
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-15 12:18:06 -08:00
James Yu
6b71013277 VP9 common for ARMv8 by using NEON intrinsics 05
Add vp9_iht4x4_add_neon.c
- vp9_iht4x4_16_add_neon

The assembly did not previously implement tx_type 0
BUG=715

Change-Id: I60034d1568de034edba45c5cdd13f3d87dbc73b6
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-15 12:16:19 -08:00
James Zern
8d558f2ca5 Merge "vp9/MACROBLOCKD: reorder struct members" 2014-12-15 11:54:51 -08:00
Paul Wilkins
91471d6aad Revert "Add support for setting byte alignment."
Fails to compile. Bad calls to vp9_alloc_frame_buffer
and vp9_realloc_frame_buffer in postproc.c

This reverts commit 399823b6f5.

Change-Id: I29f0e173f8e185d3a303cfdb17813e1eccb51e3a
2014-12-15 11:54:13 +00:00
James Zern
c58c579ec4 vp9/MACROBLOCKD: reorder struct members
improves locality of reference

Change-Id: I0639b98bf38879f918173b3a1b25dd93090e88b4
2014-12-12 18:01:24 -08:00
Frank Galligan
9c2601eb68 Merge "Add support for setting byte alignment." 2014-12-12 15:47:11 -08:00
James Zern
89ee8923a8 Merge "Remove redundant loads on 1d16_v8 filter." 2014-12-12 14:32:52 -08:00
James Zern
f82d7fd854 Merge "Remove redundant loads on 1d8_v8 filter." 2014-12-12 14:32:26 -08:00
James Zern
4d40a046da Merge "vp9: move encoder-only member from common" 2014-12-12 14:28:55 -08:00
James Zern
2bf4b4852f Merge changes Id6421838,I37499329
* changes:
  vp9: make postproc members depend on CONFIG_VP9_POSTPROC
  vp9_postproc: remove redundant CONFIG_* checks
2014-12-12 14:27:56 -08:00
Frank Galligan
399823b6f5 Add support for setting byte alignment.
Add support for setting byte alignment on the Y, U, and V plane of the
reference buffers. The byte alignment must be a power of 2, from 32 to
1024. A value of 0 sets legacy alignment.

Change-Id: I7c1399622f7aa68e123646369216b32047dda73d
2014-12-12 13:34:36 -08:00
Frank Galligan
6a24dbd71f Remove redundant loads on 1d16_v8 filter.
This CL showed about a 3% gain in performance on some systems.

Change-Id: Id27e7e0b8e69068aa364e67859436da852669250
2014-12-12 11:48:47 -08:00
Frank Galligan
44ee777905 Remove redundant loads on 1d8_v8 filter.
This CL showed a modest gain in performance on some systems.

Change-Id: Iad636a89a1a9804ab7a0dea302bf2c6a4d1653a4
2014-12-12 11:34:24 -08:00
James Zern
72ece1308b vp9: move encoder-only member from common
allow_comp_inter_inter VP9_COMMON -> VP9_COMP

Change-Id: I6d9dc25d1cdd7e2ab62f5be69cd9fa883d21dbb6
2014-12-12 11:17:44 -08:00
James Zern
ef06de33fe vp9: make postproc members depend on CONFIG_VP9_POSTPROC
Change-Id: Id64218386968cee3132269e4a0572650f20fd980
2014-12-12 11:17:17 -08:00
James Zern
890f7bedf3 vp9_postproc: remove redundant CONFIG_* checks
the entire module is wrapped in CONFIG_VP9_POSTPROC which is forcibly
enabled with CONFIG_INTERNAL_STATS

+ a similar change in vp9_alloccommon.c

Change-Id: I374993297a9fba5bef2f0b71f984eba42f0995a3
2014-12-12 11:17:16 -08:00
James Zern
d456ccbc9d vp9_loopfilter_mmx: remove some unused tables
Change-Id: I964d25cc91c8e4864d73b142d9c7a1b39cb6cfbb
2014-12-12 11:16:24 -08:00
JackyChen
3425d6c83e Merge "Multiframe Quality Enhancement(MFQE) in VP9." 2014-12-11 16:24:08 -08:00
Alexander Voronov
6c6a97814f Prevent decoder from using uninitialized entropy context.
If decoding starts with intra-only frame, there is a possibility
of using uninitialized entropy context, what leads to undefined
behavior.

Change-Id: Icbb64b5b1bd1e5de2a4bfa2884e56bc0a20840af
2014-12-11 20:44:19 +03:00
Peter de Rivaz
5c22224e9e Corrected optimization of 8x8 DCT code
The 8x8 DCT uses a fast version whenever possible.
There was a mistake in the checking code which
meant sometimes the fast version was used when it
was not safe to do so.

Change-Id: I154c84c9e2d836764768a11082947ca30f4b5ab7
(cherry picked from commit fd05fb0c21)
2014-12-11 09:42:57 -08:00
JackyChen
7ac3e3c1d6 Multiframe Quality Enhancement(MFQE) in VP9.
It is the first version of MFQE in VP9. There are a few TODOs included
in this version.
Usage: Add flag --enable-vp9-postproc to config the project.
In decoder, use flag --mfqe in the command line to enable
MFQE in postproc.
Note: Need to have key frame with low quality to see the effect of this
new patch. In my experiment, I fixed the qindex to 200 in key frame.

Change-Id: I021f9ce4616ed3574c81e48d968662994b56a396
2014-12-11 09:19:39 -08:00
James Yu
3f7c12dab9 VP9 common for ARMv8 by using NEON intrinsics 18
Add vp9_idct32x32_add_neon.c
- vp9_idct32x32_1024_add_neon

Change-Id: Ic598b772c28bd3487a8ead7a4598a66b25f9b00f
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-10 18:20:04 -08:00
James Yu
3cfed4bf76 VP9 common for ARMv8 by using NEON intrinsics 14
Add vp9_idct16x16_add_neon.c
- vp9_idct16x16_256_add_neon_pass1
- vp9_idct16x16_256_add_neon_pass2
- vp9_idct16x16_10_add_neon_pass1
- vp9_idct16x16_10_add_neon_pass2

Change-Id: I54d25b54a36f4371760f54e4036693aaea40a5de
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-10 18:19:54 -08:00
James Yu
ce76aeb00d VP9 common for ARMv8 by using NEON intrinsics 13
Add vp9_idct8x8_add_neon.c
- vp9_idct8x8_64_add_neon
- vp9_idct8x8_10_add_neon

Change-Id: I6ee7b4496765aa36ed52990f2ef73e9f24459610
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-10 14:56:54 -08:00
James Yu
8c25f4af6a VP9 common for ARMv8 by using NEON intrinsics 12
Add vp9_idct4x4_add_neon.c
- vp9_idct4x4_16_add_neon

Change-Id: I011a96b10f1992dbd52246019ce05bae7ca8ea4f
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-10 14:49:59 -08:00
James Yu
420f58f2d2 VP9 common for ARMv8 by using NEON intrinsics 11
Add vp9_idct16x16_1_add_neon.c
- vp9_idct16x16_1_add_neon

Change-Id: I7c6524024ad4cb4e66aa38f1c887e733503c39df
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-10 13:06:58 -08:00
James Yu
030ca4d0e5 VP9 common for ARMv8 by using NEON intrinsics 10
Add vp9_idct32x32_1_add_neon.c
- vp9_idct32x32_1_add_neon

Change-Id: If9ffe9a857228f5c67f61dc2b428b40965816eda
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-10 13:04:29 -08:00
James Yu
2772b45ac0 VP9 common for ARMv8 by using NEON intrinsics 09
Add vp9_idct8x8_1_add_neon.c
- vp9_idct8x8_1_add_neon

Change-Id: I9d23e01fa96013febbf64db6c76c6c955f14e3ff
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-10 12:52:33 -08:00
James Yu
9114f0afdb VP9 common for ARMv8 by using NEON intrinsics 08
Add vp9_idct4x4_1_add_neon.c
- vp9_idct4x4_1_add_neon

Change-Id: Ieab9af107dbd07a4f9503bc945890c90faccb8ac
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-10 12:49:28 -08:00
James Yu
01fc6f51e0 VP9 common for ARMv8 by using NEON intrinsics 07
Add vp9_convolve8_neon.c
- vp9_convolve8_horiz_neon
- vp9_convolve8_vert_neon

Change-Id: I0bdd99ff72d275223fe211ac7243c25a5a60cf87
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-09 20:03:07 -08:00
James Yu
893534a996 VP9 common for ARMv8 by using NEON intrinsics 04
Add vp9_convolve8_avg_neon.c
- vp9_convolve8_avg_horiz_neon
- vp9_convolve8_avg_vert_neon

Change-Id: I617971e37b02186fec5aca181f4f9622050ea2df
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-09 20:03:07 -08:00
James Yu
d12757f5c6 VP9 common for ARMv8 by using NEON intrinsics 03
Add vp9_copy_neon.c
- vp9_convolve_copy_neon

Change-Id: I291fc5423d06240876411bbceab03eae5ef585be
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-09 20:02:46 -08:00
Scott LaVarnway
617382a2e3 VP9 common for ARMv8 by using NEON intrinsics 02
Add vp9_avg_neon.c
- vp9_convolve_avg_neon

Change-Id: Id2c9d5bcfa37cff1a16417aba1656ff07bdf10fd
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-09 19:00:21 -08:00
hkuang
4eee74d6ed Fix clang ioc warning due to NULL src_mi pointer.
The warning only happens in VP9 encoder's first pass due to src_mi
is not set up yet. But it will not fail the encoder as left_mi and
above_mi are not used in the first_pass and they will be set up again
in the second pass.

Change-Id: I12dffcd5fb1002b2b2dabb083c8726650e4b5f08
2014-12-09 14:32:48 -08:00
James Yu
5b098b1825 VP9 common for ARMv8 by using NEON intrinsics 01
Add vp9_loopfilter_neon.c
- vp9_lpf_horizontal_4_neon
- vp9_lpf_vertical_4_neon
- vp9_lpf_horizontal_8_neon
- vp9_lpf_vertical_8_neon

Change-Id: I97a0d7b399a431c21ee77396be3d5f5a1f7ebccb
Signed-off-by: James Yu <james.yu@linaro.org>
2014-12-09 12:26:56 -08:00
Yunqing Wang
cddbdeabd0 Merge "SSSE3 Optimization for Atom processors using new instruction selection and ordering" 2014-12-08 13:34:54 -08:00
James Zern
c38d0490b3 Merge "Changes to assembler for NASM on mac." 2014-12-08 12:55:06 -08:00
hkuang
81e5cb86d3 Fix the comments.
Change-Id: I9789476865a1b24dad54115d8f7edb4fed780b90
2014-12-08 12:44:09 -08:00
levytamar82
8f9d94ec17 SSSE3 Optimization for Atom processors using new instruction selection and ordering
The function vp9_filter_block1d16_h8_ssse3 uses the PSHUFB instruction which has a 3 cycle latency and slows execution when done in blocks of 5 or more on Atom processors.
By replacing the PSHUFB instructions with other more efficient single cycle instructions (PUNPCKLBW + PUNPCHBW + PALIGNR) performance can be improved.
In the original code, the PSHUBF uses every byte and is consecutively copied.
This is done more efficiently by PUNPCKLBW and PUNPCHBW, using PALIGNR to concatenate the intermediate result and then shift right the next consecutive 16 bytes for the final result.

For example:
filter = 0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8
Reg = 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
REG1 = PUNPCKLBW Reg, Reg = 0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7
REG2 = PUNPCHBW Reg, Reg = 8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15
PALIGNR REG2, REG1, 1 = 0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8

This optimization improved the function performance by 23% and produced a 3% user level gain on 1080p content on Atom processors.
There was no observed performance impact on Core processors (expected).

Change-Id: I3cec701158993d95ed23ff04516942b5a4a461c0
2014-12-08 13:11:01 -07:00
hkuang
f925e5ce0f Merge "Improve the performance by caching the left_mi and right_mi in macroblockd." 2014-12-08 10:24:17 -08:00
hkuang
382f86f945 Improve the performance by caching the left_mi and right_mi in macroblockd.
This improve the deocde performance by ~2% on Nexus 7 2013.

Change-Id: Ie9c4ba0371a149eb7fddc687a6a291c17298d6c3
2014-12-05 16:25:42 -08:00
hkuang
eaa6deee5b Merge "Merge set_prev_mi function into encoder function." 2014-12-05 15:12:50 -08:00
Peter de Rivaz
a306bd8274 Use the RTC optimizations when in high bitdepth mode.
Change 72193 made the encoder behave differently
when configured with and without high bitdepth.
This change means the same algorithm is used for both.

Change-Id: I707a44a94afca773a9e0c2f7ebeeea83030257c5
2014-12-04 15:48:42 -08:00
hkuang
62de07c8c6 Merge set_prev_mi function into encoder function.
Change-Id: Ifcf2efbb232ea4cabcdebbe77e0820d121e4a6da
2014-12-04 14:44:23 -08:00
Marco
8fd3f9a2fb Enable non-rd mode coding on key frame, for speed 6.
For key frame at speed 6: enable the non-rd mode selection in speed setting
and use the (non-rd) variance_based partition.

Adjust some logic/thresholds in variance partition selection for key frame only (no change to delta frames),
mainly to bias to selecting smaller prediction blocks, and also set max tx size of 16x16.

Loss in key frame quality (~0.6-0.7dB) compared to rd coding,
but speeds up key frame encoding by at least 6x.
Average PNSR/SSIM metrics over RTC clips go down by ~1-2% for speed 6.

Change-Id: Ie4845e0127e876337b9c105aa37e93b286193405
2014-12-03 09:18:08 -08:00
Peter de Rivaz
7e40a55ef9 Added high bitdepth sse2 transform functions
Also removes some spurious changes in common/vp9_blockd.h which
was introduced by a rebase issue between nextgen and master branches.

Change-Id: If359f0e9a71bca9c2ba685a87a355873536bb282
(cherry picked from commit 005d80cd05)
(cherry picked from commit 08d2f54800)
(cherry picked from commit 4230c2306c)
2014-12-02 11:16:24 -08:00
Alex Converse
0496d11486 Fix a tautological assert.
Change-Id: I90ad08823e1d038384536fa9f458caadc2c87f38
2014-11-24 15:01:01 -08:00
Debargha Mukherjee
e9d9f1adab Merge "Refactored idct routines and headers" 2014-11-24 12:47:03 -08:00