Commit Graph

17889 Commits

Author SHA1 Message Date
Linfeng Zhang
d586cdb4d4 Remove the unnecessary cast of (int16_t)cospi_{1...31}_64
BUG=webm:1450

Change-Id: If59743aafe99226e0ec67ab5d20678ce25f53ab8
2017-09-20 14:13:26 -07:00
Linfeng Zhang
76a3d3fcc5 Remove the unnecessary upcasts of (int)cospi_{1...31}_64
BUG=webm:1450

Change-Id: Ib046fe28caec5b9ebdc9d0152df7c54ff4266858
2017-09-20 14:13:26 -07:00
Linfeng Zhang
64653fa133 Change cospi_{1...31}_64 from tran_high_t to tran_coef_t
The unnecessary upcast to (int) will be cleaned later.

BUG=webm:1450

Change-Id: Ia234575206d5a74540526924b06ed3939322d063
2017-09-20 14:13:26 -07:00
James Zern
f7b276c26b Merge "Bug fix: fadst4() in vp9/encoder/vp9_dct.c" 2017-09-20 21:12:45 +00:00
Linfeng Zhang
24afb5d036 Bug fix: fadst4() in vp9/encoder/vp9_dct.c
A new bug was introduced in a80bdfd "Change sinpi_{1,2,3,4}_9 from
tran_high_t to int16_t". Reverted the change in this file.

BUG=webm:1450

Failed test C/TransHT.AccuracyCheck/26.

Change-Id: Id001f57aad811803ef7d367d2b2bc008d8499991
2017-09-20 12:27:29 -07:00
Marco Paniconi
f407b30490 Merge "vp9: Modify simple_block_yrd condition for SVC" 2017-09-20 16:42:31 +00:00
Scott LaVarnway
b85e391ac8 Merge "vpxdsp: [x86] add highbd_d63_predictor functions" 2017-09-20 11:39:28 +00:00
James Zern
15bea62176 temporal_filter_apply_sse2.asm: add ':' to label
quiets nasm warning:
label alone on a line without a colon might be in error

BUG=webm:1462

Change-Id: I660407ca60e8c9a810dba9d76afb65852029a29c
2017-09-19 18:59:11 -07:00
Linfeng Zhang
7c0529728a cosmetics: NEON scaling code
Change-Id: Ib91054622c1f09c4ca523bc6837d7d8ab9f03618
2017-09-19 16:39:17 -07:00
Linfeng Zhang
f357335c38 Refactor convolve NEON code
Rename a couple of hbd static functions.
Move the position of NEON function convolve8_4().

Change-Id: Idfac00edf2e99cdd8e0a73b9f895402f60be6349
2017-09-19 16:28:36 -07:00
Linfeng Zhang
bf8bdae913 Refactor convolve code
Extract a couple of static functions into their caller functions.

Change-Id: If8d8a0e217fba6b402d2a79ede13b5b444ff08a0
2017-09-19 16:28:31 -07:00
Scott LaVarnway
bc86e2c6a2 vpxdsp: [x86] add highbd_d63_predictor functions
C vs SSE2 speed gains:
_4x4 : ~2.94x

C vs SSSE3 speed gains:
_8x8 : ~8.69x
_16x16 : ~6.32x
_32x32 : ~5.33x

BUG=webm:1411

Change-Id: I2c35b527eac2229f17aaa9d118fb601e7195efe4
2017-09-19 15:47:22 -07:00
Marco
aaa6cdcc2e vp9: Modify simple_block_yrd condition for SVC
Modify simple_block_yrd condition in nonrd_pickmode for SVC:
allow it to be used also on base temporal_layer, only when
spatial_layer > 1 and block size < 32x32.

Speed up of about ~2% for 3 layer SVC, with little/negligible
loss in quality.

Change-Id: I7734bdae51cf51f22b96f6b2b27da20ea1d84344
2017-09-19 15:39:05 -07:00
Marco Paniconi
2a7c0e1c4b Merge "Add datarate test for frame_parallel_decoding mode off." 2017-09-19 22:31:08 +00:00
Marco
cd463c7acb vp9: Fix condition for limiting ARF 1 pass vbr.
Fix the setting to frames_till_gf_update_due, and
adjust the limit value.
Only affects when USE_ALTREF_FOR_ONE_PASS is enabled.

Neutral change to metrics and speed for ytlive.

Change-Id: I266d9a00b36221bc8602fa2746d4e8a8f7d4dfae
2017-09-19 11:12:37 -07:00
Marco Paniconi
310e388423 Merge "vp9: Adjustments for ARF usage in 1 pass vbr." 2017-09-19 16:29:19 +00:00
Marco
ebb015a539 vp9: Adjustments for ARF usage in 1 pass vbr.
Only when USE_ALT_REF_ONE_PASS is enabled (off by default).
Force fixed partition to 64x64 when is_src_alt_ref_frame is true,
and don't force early exit for some modes in nonrd_pickmode
for ARF noshow frames.

Small gain ~0.2% on ytlive metrics for speed 6.
Neutral speed difference.

Change-Id: I27eb6622d0453c09a06ccdc3b16368762474d11d
2017-09-18 18:46:41 -07:00
Linfeng Zhang
a80bdfd081 Change sinpi_{1,2,3,4}_9 from tran_high_t to int16_t
Add "typedef int16_t tran_coef_t;"

BUG=webm:1450

Change-Id: I67866f104898d1dda8989e1abdaf6983fe324154
2017-09-18 09:26:03 -07:00
Linfeng Zhang
9d278465b5 Merge "cosmetics: vp9_rtcd_defs.pl" 2017-09-18 16:23:33 +00:00
Shiyou Yin
2aacfa1acd Merge "vp8: [loongson] optimize dequantize with mmi" 2017-09-15 23:53:40 +00:00
Marco
ad31fe36a8 Add datarate test for frame_parallel_decoding mode off.
Add datarate test, for both VBR and CBR mode, with the
frame_parallel_decoding mode disabled (and error_resilience off).

Change-Id: I54feec3248a68ecff4bef8d9a31bb1616fab77df
2017-09-15 11:38:38 -07:00
Paul Wilkins
65f1c90652 Merge "Fix bug in intra mode rd penalty." 2017-09-15 15:43:29 +00:00
Kaustubh Raste
08fda52e18 Merge "mips msa clean-up msa macros" 2017-09-15 01:27:02 +00:00
James Zern
90ed0d2f73 Merge "vp9_scale_test: add C config" 2017-09-15 00:27:58 +00:00
James Zern
c12b39626f Merge "Revert "Specialize 4 to 3 scaling in vp9_scale_and_extend_frame_c()"" 2017-09-15 00:27:41 +00:00
Hui Su
293734b755 Merge "VP9 level targeting: add a new AUTO mode" 2017-09-14 21:02:38 +00:00
James Zern
c24d911847 vp9_scale_test: add C config
Change-Id: I9dfe8255d1c096d246bf9719729f57dbae779ffc
2017-09-14 13:08:04 -07:00
James Zern
baf658ec4c Revert "Specialize 4 to 3 scaling in vp9_scale_and_extend_frame_c()"
This reverts commit afee58f2c4.

This causes ~8x slowdown in 4:3 in the C-code

Change-Id: I60a7ead12dc4ec1548b1b12cfe4b0be42ef04e0e
2017-09-14 13:07:21 -07:00
Hui Su
c3a6943c16 VP9 level targeting: add a new AUTO mode
In the new AUTO mode, restrict the minimum alt-ref interval and max column
tiles adaptively based on picture size, while not applying any rate control
constraints.

This mode aims to produce encodings that fit into levels corresponding to
the source picture size, with minimum compression quality lost. However, the
bitstream is not guaranteed to be level compatible, e.g., the average bitrate
may exceed level limit.

BUG=b/64451920

Change-Id: I02080b169cbbef4ab2e08c0df4697ce894aad83c
2017-09-14 16:20:29 +00:00
Shiyou Yin
b81de66171 vp8: [loongson] optimize dequantize with mmi
1. vp8_dequantize_b_mmi
2. vp8_dequant_idct_add_mmi

Change-Id: I505f8afb7a444173392b325906e6a4f420f00709
2017-09-14 20:56:06 +08:00
Shiyou Yin
5b558592f5 vp8: [loongson] optimize idctllm with mmi
1. vp8_short_idct4x4llm_mmi
2. vp8_short_inv_walsh4x4_mmi
3. vp8_dc_only_idct_add_mmi

Change-Id: I616923681e79d78607a4988608fc39df77b093f4
2017-09-14 16:51:11 +08:00
Kaustubh Raste
4ca8f8f5e2 mips msa clean-up msa macros
Removed inline for GP load-store in case of (__mips_isa_rev >= 6)
Created one define LD_V for vector load and ST_V for vector store

Change-Id: Ifec3570fa18346e39791b0dd622892e5c18bd448
2017-09-14 12:29:19 +05:30
Linfeng Zhang
535dee0fb6 cosmetics: vp9_rtcd_defs.pl
Change-Id: I1bf57824e07fa4f8b3b5574984117f2bd7a1c086
2017-09-13 12:13:55 -07:00
Linfeng Zhang
0726dd97d3 Merge "Specialize 4 to 3 scaling in vp9_scale_and_extend_frame_c()" 2017-09-13 17:21:45 +00:00
Andrew Lewis
949730e2dc Comma-separate VP9 encoder tmp.stt output
Also add column headings so that the output can still be parsed if the
set of headers changes later.

Change-Id: I4beaf266521e093db4acf5f715b18fdfb7e3d1cd
2017-09-13 16:26:40 +01:00
Johann Koenig
ed3a80cb5e Merge "Revert "Revert "quantize avx: copy 32x32 implementation""" 2017-09-13 14:44:53 +00:00
Kaustubh Raste
83e59914e5 Merge "Optimize mips msa vp9 average mc functions" 2017-09-13 06:02:49 +00:00
Shiyou Yin
fa01426ade Merge "vp8: [loongson] optimize loopfilter with mmi" 2017-09-13 01:05:46 +00:00
Johann
eb4238ac70 Revert "Revert "quantize avx: copy 32x32 implementation""
This reverts commit 8c42237bb2.

Because ssse3 code is used for the reference, the qcoeff and dqcoeff
reference buffers must be aligned.

Original change's description:
> quantize avx: copy 32x32 implementation
>
> Ensure avx and ssse3 stay in sync by testing them against each other.
>
> Change-Id: I699f3b48785c83260825402d7826231f475f697c

Change-Id: Ieeef11b9406964194028b0d81d84bcb63296ae06
2017-09-12 14:25:38 -07:00
Linfeng Zhang
afee58f2c4 Specialize 4 to 3 scaling in vp9_scale_and_extend_frame_c()
Scale 3x3 block instead of 16x16 block in each loop.

Benefits:
1. Reduced number of different phase_scaler from 16 to 3. Optimization code
   will be smaller and faster.
2. The maximum phase_scaler drifting will be reduced from 5/16 to 1/24.
   (The drifting is 1/(3*16) in each step.)

BUG=webm:1419

Change-Id: Ibb9242a629ddb03e1ff93b859bece738255e698c
2017-09-12 12:05:16 -07:00
Kaustubh Raste
30f1ff94e0 Optimize mips msa vp9 average mc functions
Load the specific destination loads instead of vector load

Change-Id: I65ca13ae8f608fad07121fef848e2a18f54171fe
2017-09-12 16:12:11 +05:30
Scott LaVarnway
c39cd9235e Merge "vpxdsp: [x86] add highbd_d207_predictor functions" 2017-09-11 22:32:23 +00:00
Linfeng Zhang
a9bbe53dbb Add 4 to 1 scaling NEON optimization
BUG=webm:1419

Change-Id: If82a93935d2453e61b7647aae70983db1740bec7
2017-09-11 10:17:28 -07:00
Scott LaVarnway
d6c9bbc2b6 vpxdsp: [x86] add highbd_d207_predictor functions
C vs SSE2 speed gains:
_4x4 : ~2.31x

C vs SSSE3 speed gains:
_8x8 : ~4.73x
_16x16 : ~10.88x
_32x32 : ~4.80x

BUG=webm:1411

Change-Id: I0bac29db261079181ddabc6814bd62c463109caf
2017-09-11 07:36:24 -07:00
Shiyou Yin
761f2f5cb4 vp8: [loongson] optimize loopfilter with mmi
1. vp8_loop_filter_horizontal_edge_mmi
2. vp8_loop_filter_vertical_edge_mmi
3. vp8_mbloop_filter_horizontal_edge_mmi
4. vp8_mbloop_filter_vertical_edge_mmi
5. vp8_loop_filter_simple_horizontal_edge_mmi
6. vp8_loop_filter_simple_vertical_edge_mmi

Change-Id: Ie34bbff3a16cff64e39a50798afd2b7dac9bcdc3
2017-09-11 11:08:09 +08:00
James Zern
fb40b5d7a7 intrapred: sync highbd_d63_predictor w/d63_
8/16/32: ~6%/~18%/~33% faster

previously:
7012ba639 vp9_reconintra: simplify d63_predictor

BUG=webm:1411

Change-Id: Ie775f3a4f7fd74df44754e65686d826a51c2cdc2
2017-09-08 19:28:01 -07:00
James Zern
9dfa76f948 vpx_mem: make vpx_memset16 inline
Change-Id: Ibb2cab930c95836e6d6e66300c33e7d08e4474d4
2017-09-08 19:11:46 -07:00
James Zern
5c95fd921e intrapred: sync highbd_d45_predictor w/d45_
8/16/32:: ~19%/~54%/~75.5% faster

previously:
acc481eaa vp9_reconintra: simplify d45_predictor

BUG=webm:1411

Change-Id: Ie8340b0c5070ae640f124733f025e4e749b660d8
2017-09-08 19:09:07 -07:00
James Zern
9a2dd7e67e Merge changes I9ec438aa,I99c954ff
* changes:
  Update convolve functions' assertions
  Add 2 to 1 scaling NEON optimization
2017-09-08 19:23:40 +00:00
paulwilkins
0657f4732c Fix bug in intra mode rd penalty.
The intra mode rd penalty was implemented as a rate penalty.
Code was added to scale the penalty according to block size but
this was not done correctly for the SB level or sub 8x8.

The code did a weird double scaling in regard to bit depth that
has been removed. Given that it is a rate penalty the bit depth
should not matter.

This bug fix improves average metrics  on our standard test
sets by about 0.1%

Change-Id: I7cf81b66aad0cda389fe234f47beba01c7493b1e
2017-09-08 15:10:53 +01:00