Commit Graph

13575 Commits

Author SHA1 Message Date
Parag Salasakar
f1b09c0433 Merge "mips msa vp9 convolve8 avg horiz optimization" 2015-06-04 01:16:21 +00:00
Marco
a8c5ab2ca6 Remove ABI check for 1 pass CBR SVC.
Remove the ABI check for the controls needed for SVC 1 pass CBR mode.
Bump up the ABI version.

Change-Id: I35b79ee010e14af83c6d1e801d574deaaa2fc7eb
2015-06-03 17:43:22 -07:00
hkuang
98e88e6ad8 Optimize the idct assembly code.
Change-Id: Ia0ff859ff1c813dbe100e2f27b1ef78167483f4e
2015-06-03 17:20:35 -07:00
Paul Wilkins
668e804504 Animation and dead zone detection.
Adds code to detect dead zone bars at the top and bottom
of reformatted letterbox video (note that the code only
looks at the top of the image and assumes any dead zone
is symmetrical).  Use of this to adapt rate control etc.
will follow in a subsequent patch.

Also counts other blocks (excluding the dead zone) that
have no intra signal. The presence of a significant
number of such blocks can be used as a identify that the frame
may be artificial (e.g.  animation, screen capture, graphics).
This patch contains plumbing only and does not use
the signal.

Change-Id: I59bc93529cd4065416cef773e405fda3ae006a20
2015-06-04 01:01:20 +01:00
Marco
5df6c04585 Fix to sample encoder: vpx_temporal_svc_encoder.c
vp8 uses ts_target_bitrate for layer settings.

Change-Id: Ie72477b549051396feebff87a3744fed04366bf4
2015-06-03 14:50:27 -07:00
Johann
ce2ca9f777 Duplicate reference variance code
Some places are using the unoptimized variance function. This was never
intended and does not fit into the optimization framework.

Change-Id: Id96238407aad03b0ffd4a46cd183555a026daedc
2015-06-03 13:28:59 -07:00
Johann
516c087c51 Remove unused sub pixel mse
Change-Id: I7a5e4e2632c3fa69d2a85a68fa9b418631caf09c
2015-06-03 08:00:51 -07:00
Parag Salasakar
b8c1cdcd12 mips msa vp9 convolve8 avg horiz optimization
average improvement ~5x-8x

Change-Id: I179a69ec620fbd69979bd128f05d18113618aab4
2015-06-03 11:33:42 +05:30
Parag Salasakar
179bceffdb Merge "mips msa vp9 convolve8 avg vert optimization" 2015-06-03 05:58:43 +00:00
James Zern
0601f92a88 Merge "test-data.sha1: mark test data files as binary" 2015-06-03 05:49:43 +00:00
James Zern
88fadafa9e Merge "Support building shared libraries on OS/2" 2015-06-03 05:47:43 +00:00
KO Myung-Hun
19dbc0f066 test-data.sha1: mark test data files as binary
Change-Id: Ie3605bf4c4fb16eb21186adbb4577c20a8027344
2015-06-03 13:48:35 +09:00
KO Myung-Hun
6d52fe2e71 Support building shared libraries on OS/2
Change-Id: I5750db0504cb69ead52f9f44bf583e693bffbb7e
2015-06-03 13:48:34 +09:00
Parag Salasakar
c543d38ac7 mips msa vp9 convolve8 avg vert optimization
average improvement ~4x-6x

Change-Id: Ia2e6f770da46416ebec31fdcea5cc7878879a9d9
2015-06-03 09:55:25 +05:30
Parag Salasakar
622beaba67 Merge "mips msa vp9 idct4x4 and iwht4x4 optimization" 2015-06-03 04:10:14 +00:00
Johann
01853d7ce9 Merge "Unify reference variance functions" 2015-06-03 02:03:45 +00:00
Johann
d90536c1a2 Unify reference variance functions
Use uint32_t for all output and make all functions static

Change-Id: I2c9c6f6310732dc53444607d1c1a268ac1ab83ba
2015-06-02 15:14:55 -07:00
Johann
e2a5fd2cf4 Merge "Disable neon bilinear 4x4" 2015-06-02 21:44:14 +00:00
Scott LaVarnway
f779dba405 Remove counts param
Moved to MACROBLOCKD.

Change-Id: Icce765b334f2755f4fe2a4c39fb2ae2d7660d004
2015-06-02 09:06:00 -07:00
Marco
c139b81a13 Vidyo patch: Rate control for SVC, 1 pass CBR mode.
-Make Rate control work for SVC 1 pass CBR mode.
-Added temporal layering mode.
-Fixed bug in non-rd variance partition.
-Modified/updated the sample encoders (vp9_spatial_svc_encoder, vpx_temporal_svc_encoder).
-Added datarate unittest(s) for 1 pass CBR SVC.

Change-Id: Ie94b1b68a56ea1267b5087c625e5df04def2ee48
2015-06-02 07:54:13 -07:00
Parag Salasakar
54a6f73958 mips msa vp9 idct4x4 and iwht4x4 optimization
average improvement ~3x-4x
moved assert to respective files

Change-Id: I6c915059d456a00bdd76fab0dd2eede8b6c6ea58
2015-06-02 12:16:28 +05:30
Parag Salasakar
ebf7466cd8 mips msa vp9 updated convolve horiz, vert, hv, copy, avg module
Updated sources according to improved version of common MSA macros.
Enabled respective convolve MSA hooks and tests.
Overall, this is just upgrading the code with styling changes.

Change-Id: If5ad6ef8ea7ca47feed6d2fc9f34f0f0e8b6694d
2015-06-02 12:03:51 +05:30
Parag Salasakar
cf1c0ebc3a Merge "mips msa vp9 updated idct 8x8, 16x16 and 32x32 module" 2015-06-02 04:48:02 +00:00
Johann
86d0cb8325 Disable neon bilinear 4x4
Clang adds alignment hints when casting up the loads/stores. Although
this should be safe for most paths, it's causing some crashes. Either
the source of the misalignment needs to be determined and adjusted or
the intrinsics need to be rewritten to avoid using the cast to load the
data.

BUG=817,892

Change-Id: Ia3aa824d6a4cd97e14325ff49dc730b6f85ec7e8
2015-06-02 00:02:55 +00:00
Johann Koenig
cbebbff025 Merge "Adds subsecond frame rates to webm" 2015-06-01 22:36:09 +00:00
James Zern
71d923232c Merge changes from topic 'vp9-intra-pred'
* changes:
  vp9_reconintra_neon/tm: improve above_left load
  vp9_reconintra_neon: cosmetics: normalize fn params
2015-06-01 20:03:47 +00:00
James Zern
b601202905 Merge "vp9_reconintra_neon_asm/tm: simplify above_left load" 2015-06-01 20:01:38 +00:00
Johann
275c102787 Merge "Cast variance reference output" 2015-06-01 18:56:50 +00:00
paulwilkins
dbd3760712 Merge "Fast feedback of bits on undershoot." 2015-06-01 18:15:10 +00:00
Johann
fdc549994a Cast variance reference output
The larger internal variables are required for the intermediates
but RoundHighBitDepth brings them down to uint32_t/unsigned int.

Fixes type warnings in visual studio.

Change-Id: I48d35284d6cbde330ccdc1f46b6215a645d5eb00
2015-06-01 10:56:52 -07:00
Johnny Klonaris
d02aa04422 Adds subsecond frame rates to webm
Numerator was being range checked against the
denominator - preventing any frame rate slower
than 1 fps.

I've tested this on a Mac using using ffmpeg and
results are comparable to mp4 and ogg files generated
at the same time.

Not yet tested on Windows.

Johnny Klonaris
google@jawknee.com

Change-Id: Idb358dbc2e7dc000037880ede4a1b0df248a42c8
2015-06-01 10:13:58 -07:00
Parag Salasakar
6af9d7f2e2 mips msa vp9 updated idct 8x8, 16x16 and 32x32 module
Updated sources according to improved version of common MSA macros.
Enabled idct MSA hooks and tests.
Overall, this is just upgrading the code with styling changes.

Change-Id: I1f488ab2c741f6c622b7a855388a202168082209
2015-06-01 09:24:23 +05:30
James Zern
acc481eaae vp9_reconintra: simplify d45_predictor
only the immediate above right pixel is needed; this removes a
conditional from the inner loop
the final average calculated currently relies on above[] being extended,
it could be reduced to use above[block_size - 2] + 3 * above_right

Change-Id: Ica4f2b8d25eec3ca1d6fa52ef0d4adc228eeea3f
2015-05-30 13:30:59 -07:00
James Zern
6e068e51b5 vp9_reconintra: specialize d135 4x4
based on webp's RD4()

Change-Id: I64c8f0a1325a8f201eaad39b396fae7a2d06efff
2015-05-30 13:29:40 -07:00
James Zern
b6782686f4 vp9_reconintra: specialize d117 4x4
based on webp's VR4()

Change-Id: Ic8c0b8ed65a63772ca0a4321592880a5e8947db5
2015-05-30 13:29:02 -07:00
James Zern
c022dbc4d3 vp9_reconintra: specialize d207 4x4
based on webp's HU4()

Change-Id: I2401ef307cd94e70cc7904f55954af04290c8af9
2015-05-30 13:28:22 -07:00
James Zern
2276eb16f3 vp9_reconintra: specialize d153 4x4
based on webp's HD4()

Change-Id: Icba1e21ec4b8f5026dc92e49741a68b059c8b9b1
2015-05-30 13:27:50 -07:00
James Zern
102123821d vp9_reconintra: specialize d63 4x4
based on webp's VL4()

Change-Id: Ibab962053843eae8752b4e74b6481a53bb034ae9
2015-05-30 13:27:03 -07:00
James Zern
6051bcc3dc vp9_reconintra: specialize d45 4x4
based on webp's LD4()

Change-Id: I74855d23ce73e1c6988fe08bf7c959b7a69b4abf
2015-05-30 13:26:21 -07:00
Parag Salasakar
71e88f903d Merge "mips msa vp9 updated macros and disable all MSA functions" 2015-05-30 02:52:27 +00:00
James Zern
7621b48a1c vp9_reconintra_neon/tm: improve above_left load
use vld1?_dup_u8 over vdup?_n_u8, reduces general register use; mildly
faster

Change-Id: Ie0e4e550849a207b34b378541196b553c9f12011
2015-05-29 19:18:43 -07:00
James Zern
f2d621e383 vp9_reconintra_neon: cosmetics: normalize fn params
s/y_stride/stride/

Change-Id: Ie98c3fe241dc240b653849eda356a8862bdd52f4
2015-05-29 19:01:39 -07:00
James Zern
b337c54cc4 vp9_reconintra_neon_asm/tm: simplify above_left load
use vld1.8 {d0[]}, [r0] rather than ldrb+vdup; mildly faster

Change-Id: I5c24d49a90c2855c94395184774b289da8e9d5a7
2015-05-29 18:56:16 -07:00
James Zern
7544e766e4 Merge changes from topic 'vp9-intra-pred'
* changes:
  vp9_reconintra_neon: add DC 16x16 predictors
  vp9_reconintra_neon: add DC 8x8 predictors
2015-05-30 01:51:35 +00:00
James Zern
a2a13cbe5f vp9_reconintra_neon: add DC 16x16 predictors
85-89% faster over 20M pixels

Change-Id: I9b320ed6b9e67f27df738b84c8b43b65a93c50c2
2015-05-29 15:41:44 -07:00
James Zern
e97b849219 vp9_reconintra_neon: add DC 8x8 predictors
~90% faster over 20M pixels

Change-Id: Iab791510cc57c8332c2f9a5da0ed50702e5f5763
2015-05-29 15:39:08 -07:00
Parag Salasakar
f9f078ebb6 mips msa vp9 updated macros and disable all MSA functions
Done little restructuring/styling changes to the sources like generic macro definitions, their use to reduce code lines, better code alignments etc.
Disabled all MSA hooks and tests

Change-Id: Ic6f2dce0b501f46b80c06c46c0fe2043d557b190
2015-05-29 13:34:33 +05:30
James Zern
be380f2005 variance_neon: add missing include
vpx_ports/mem.h is necessary for MSVC __builtin_prefetch compatibility
macro

Change-Id: I210fad6c6b4545df1874d028b31f42018490b029
2015-05-28 23:38:53 -07:00
Marco
26ab314176 For non-rd pickmode: remove VAR_PARTITION condition.
Keep the logic, transform size based on cyclic refresh and bsize,
(that was conditioned on VAR_PARTITION conditions) the same
for all speeds in non-rd mode (speeds >= 5).

No change to speeds >=6.
Small improvement for speed 5, ~0.5/1.5% gain for avg psnr/ssim.

Change-Id: If9c5657f3d30efd3c7f147166bba7cb69ea55114
2015-05-28 17:29:47 -07:00
Minghai Shang
45db29784d Merge "[svc] Disable tiles for spatial svc case" 2015-05-28 22:13:54 +00:00