Disable unit-tests. The logging in GTest would need to be adjusted.
Restructure ARM cpu detection. Flatten if-else logic.
Change #if defined(HAVE_*) to #if HAVE_* because we only need to check
for features that the library was actually built with. This should have
been harmless, as disabled feature sets wouldn't have any features to
call.
Change-Id: Iea21aa42ce5f049c53ca0376d25bcd0f36f38284
Soft enable runtime cpu detect for armv7-android target, so that it
can be disabled and remove dependency on 'cpufeatures' lib.
Change the arm_cpu_caps implementation selection such that 'no rtcd' takes
precedence over system type.
Switch to use -mtune instead of -mcpu. NDK was complaining about
-mcpu=cortex-a8 conflicting with -march=armv7-a, not sure why.
Add a linker flag to fix some cortex-a8 bug, as suggested by NDK Dev
Guide.
Examples:
Configure for armv7+neon:
./configure --target=armv7-android-gcc \
--sdk-path=/path/to/android/ndk \
--disable-runtime-cpu-detect \
--enable-realtime-only \
--disable-unit-tests
...armv7 w/o neon:
./configure --target=armv7-android-gcc \
--sdk-path=/path/to/android/ndk \
--disable-runtime-cpu-detect \
--enable-realtime-only \
--disable-neon \
--cpu=cortex-a9 \
--disable-unit-tests
Change-Id: I37e2c0592745208979deec38f7658378d4bd6cfa
A processor with ARMv7 instructions does not
necessarily have NEON dsp extensions. This CL
has the added side effect of allowing the ability
to enable/disable the dsp extensions cleanly.
Change-Id: Ie1e879b8fe131885bc3d4138a0acc9ffe73a36df
Android.mk file for using the Android NDK build
system to compile. Adds option for SDK path to
use the compiler that comes with android for testing
compiler compliance.
Change-Id: I5fd17cb76e3ed631758d3f392e62ae1a050d0d10
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
