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Author	SHA1	Message	Date
Erik Niemeyer	9f26861147	Support for extended feature flags enumeration leaf in CPUID instruction This CL fixes an overcite with the AVX2 support CL previously merged (Change-Id: Idc03f3fca4bf2d0afd33631ea1d3caf8fc34ec29) that prevented runtime execution of AVX2 code in WebM. Background: Starting with the Sandybridge processor, the CPUID instruction was enhanced to add various extended feature flag enumeration leaves. Reading these leaves requires an additional input value for the CPUID instruction which is stored in ECX. This change adds this second input value for all ARCH_X86 and ARCH_x86_64 targets to the CPUID macros, allowing checks of EBX bit 5 for AVX2 support. This capability will be required moving forward to check for future processor features. Change-Id: Ie9d872bc9ff68dad4b6578e4544e4dfd0ae26c36	2013-11-20 11:10:54 -08:00
John Koleszar	c6b9039fd9	Restyle code Approximate the Google style guide[1] so that that there's a written document to follow and tools to check compliance[2]. [1]: http://google-styleguide.googlecode.com/svn/trunk/cppguide.xml [2]: http://google-styleguide.googlecode.com/svn/trunk/cpplint/cpplint.py Change-Id: Idf40e3d8dddcc72150f6af127b13e5dab838685f	2012-07-17 11:46:03 -07:00
Fritz Koenig	0f5c63e4f6	Add processor dectection for x86. Use cpuid to check the vendor string against known architectures. Change-Id: I3fbd7f73638d71857a0c4a44a6275eb295fb4cef	2010-10-13 09:58:15 -07:00

Author

SHA1

Message

Date

Erik Niemeyer

9f26861147

Support for extended feature flags enumeration leaf in CPUID instruction

This CL fixes an overcite with the AVX2 support CL previously
merged (Change-Id: Idc03f3fca4bf2d0afd33631ea1d3caf8fc34ec29) that
prevented runtime execution of AVX2 code in WebM. 

Background:
Starting with the Sandybridge processor, the CPUID instruction was
enhanced to add various extended feature flag enumeration leaves.
Reading these leaves requires an additional input value for the CPUID
instruction which is stored in ECX. This change adds this second input
value for all ARCH_X86 and ARCH_x86_64 targets to the CPUID macros,
allowing checks of EBX bit 5 for AVX2 support. This capability will be
required moving forward to check for future processor features.

Change-Id: Ie9d872bc9ff68dad4b6578e4544e4dfd0ae26c36

2013-11-20 11:10:54 -08:00

John Koleszar

c6b9039fd9

Restyle code

Approximate the Google style guide[1] so that that there's a written
document to follow and tools to check compliance[2].

[1]: http://google-styleguide.googlecode.com/svn/trunk/cppguide.xml
[2]: http://google-styleguide.googlecode.com/svn/trunk/cpplint/cpplint.py

Change-Id: Idf40e3d8dddcc72150f6af127b13e5dab838685f

2012-07-17 11:46:03 -07:00

Fritz Koenig

0f5c63e4f6

Add processor dectection for x86.

Use cpuid to check the vendor string against known
architectures.

Change-Id: I3fbd7f73638d71857a0c4a44a6275eb295fb4cef

2010-10-13 09:58:15 -07:00

3 Commits