Replaced vpx_d45_predictor_4x4_ssse3(), vpx_d45_predictor_8x8_ssse3()
and vpx_d207_predictor_4x4_ssse3() with
created vpx_d45_predictor_4x4_sse2(), vpx_d45_predictor_8x8_sse2()
and vpx_d207_predictor_4x4_sse2() respectively.
It's mostly neutral or slightly worse than ssse3 in good cases and
better than ssse3 in the bad cases (but still worse than using the mmx
regs).
Change-Id: Ib0237ceb71d2c57b8a93fd3170330cfed9d56bdd
Use the same rounding method that is used throughout the codebase,
where the halfway value is rounded up rather than down.
Change-Id: I04e92850bc69a7d7a07b06e3d2ce97f6f2ada321
Skip intra-mode and some inter-modes (newmv, nearmv, nearestmv) for
golden frame if the variance got from choose_partitioning is very low.
Only for 1 pass real-time CBR mode and bsize >= 32x32, it has ~2.5%
speed up with less than 0.1% PSNR drop for rtc test set. Don't see
visual regression.
Change-Id: I70efbc95a1007231ae36f02c5b2fbf6cd35077ad
Reduce operations and jumps. perf shows CPU time reduced from 1.9% to
1.6% when decoding fdJc1_IBKJA.248.webm on Xeon E5.
Will apply the changes to vp10 after code review.
Change-Id: I9351509922855d8896ddef1ed093b3ca12619a61
Seperate prediction mode and tx type search for inter
modes. Enabled for speed >=1.
baseline:
speed increase 40%
compression drop 0.30%/0.29% on lowres/midres
ext-tx:
speed increase 160%
compression drop 1.08%/0.95% on lowres/midres
Change-Id: Ieb34b1ee80df6980d16e26a5783e08cc0deae55b
Add a speed feature to seperate prediction mode and tx type search
for intra modes: search for best intra prediction mode with fixed
default tx type first, then choose the best tx type for the
selected mode.
Coding performance drop:
baseline
lowres 0.10% midres 0.08% hdres 0.14%
with ext-tx
lowres 0.14% midres 0.25% hdres 0.20%
Speed improvement is 20% for baseline and 17% for ext-tx.
It is turned on for speed >= 1.
Change-Id: Ia5e8d39e8a4e2e42c521bfde938f8b6a98ab24f9
For non-rd pickmode:
best_pred_sad, computed for NEWMV-last, is only used for
skipping golden non-zero modes. Add condition to avoid this
computation if not used (i.e, if golden nonzero modes are not used).
And remove code for computing best_pred_sad for NEWMV-golden,
since that sad is not used.
No change in behavior; small speed gain (~1%) for svc encodes.
Change-Id: Ic2cbdef6c4e9a233a57c0db0eeac8ad5fcead366
This is for the bidir-pred experiment. Previously the length of the
bi-predictive frame group interval is fixed at 2, i.e. one
bi-predictive frame may be inserted every other frame. This patch
makes the length adjustable, i.e. any positive number may be
specified, but the use of the backward ref will be turned off if the
bi-predictive frame group interval is larger than the golden frame
group.
Further, an additional rate factor level has been added:
INTER_LOW
, which applies to LAST_BIPRED_UPDATE frames that are not used as
references.
Change-Id: I5514d34a64dd486bbb5756c2d0612946f598a789
convert the random value to int16 before subtracting 256 from it; quiets
a ubsan (sanitize=integer) warning
BUG=webm:1225
Change-Id: Ibc2c5a21f30e112bd6c180f7d6a033327c38d0df
Function level timing test shows about 27% time saving on
a Xeon E5-2680 v2 desktop.
Rename vp9_dct_sse2.c to vp9_dct_intrin_sse2.c for vp9 and
rename dct_sse2.c to dct_intrin_sse2.c for vp10 to avoid
duplicate basenames.
Actually vp9_fwht4x4_mmx/sse2() and vp10_fwht4x4_mmx/sse2()
are identical. TODO: They should be unified later if there is
no intention to keep a duplicate.
Change-Id: I3e537b7bbd9ba417c606cd7c68c4dbbfa583f77d
C does not allow for shifting into the sign bit of a signed
integer, and the two instances here become signed ints via
promotion. Explcitly cast them to unsigned MEM_VALUE_T to
avoid the problem.
BUG=https://bugs.chromium.org/p/chromium/issues/detail?id=614648
Change-Id: I51165361a8c6cbb5c378cf7e4e0f4b80b3ad9a6e
input_, ref_input_ and output_ were being allocated with new[] followed
by vpx_memalign, remove the former
Change-Id: Ia16d0f9b9317042a24445095ad3c284f4e7bb481
Followed the code style of other lpf fuctions.
These 2 functions put 2 rows of data in a single xmm register,
so they have similar but not identical filter operations,
and cannot share the same macros.
Change-Id: I3bab55a5d1a1232926ac8fd1f03251acc38302bc
- Avoid excessive copying
- Don't both searching if no update can possibly offer savings
- Simplify the interface
- Remove the confusing vp9_cost_upd256 macro
Change-Id: Id9d9676a361fd1203b27e930cd29c23b2813ce59
