ARMv6 optimized fdct4x4
Optimized fdct4x4 (8x4) for ARMv6 instruction set. - No interlocks in Cortex-A8 pipeline - One interlock cycle in ARM11 pipeline - About 2.16 times faster than current C-code compiled with -O3 Change-Id: I60484ecd144365da45bb68a960d30196b59952b8
This commit is contained in:
Tero Rintaluoma
parent
185557344a
commit
a61785b6a1
@ -59,9 +59,9 @@ void vp8_arch_arm_encoder_init(VP8_COMP *cpi)
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cpi->rtcd.variance.get4x4sse_cs = vp8_get4x4sse_cs_c;*/
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/*cpi->rtcd.fdct.short4x4 = vp8_short_fdct4x4_c;
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cpi->rtcd.fdct.short8x4 = vp8_short_fdct8x4_c;
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cpi->rtcd.fdct.fast4x4 = vp8_fast_fdct4x4_c;
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cpi->rtcd.fdct.fast8x4 = vp8_fast_fdct8x4_c;*/
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cpi->rtcd.fdct.short8x4 = vp8_short_fdct8x4_c;*/
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cpi->rtcd.fdct.fast4x4 = vp8_fast_fdct4x4_armv6;
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cpi->rtcd.fdct.fast8x4 = vp8_fast_fdct8x4_armv6;
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cpi->rtcd.fdct.walsh_short4x4 = vp8_short_walsh4x4_armv6;
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/*cpi->rtcd.encodemb.berr = vp8_block_error_c;
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262
vp8/encoder/arm/armv6/vp8_fast_fdct4x4_armv6.asm
Normal file
262
vp8/encoder/arm/armv6/vp8_fast_fdct4x4_armv6.asm
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@ -0,0 +1,262 @@
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;
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; Copyright (c) 2011 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vp8_fast_fdct4x4_armv6|
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ARM
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REQUIRE8
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PRESERVE8
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AREA |.text|, CODE, READONLY
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; void vp8_short_fdct4x4_c(short *input, short *output, int pitch)
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|vp8_fast_fdct4x4_armv6| PROC
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stmfd sp!, {r4 - r12, lr}
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; PART 1
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; coeffs 0-3
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ldrd r4, r5, [r0] ; [i1 | i0] [i3 | i2]
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ldr r10, c7500
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ldr r11, c14500
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ldr r12, c0x22a453a0 ; [2217*4 | 5352*4]
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ldr lr, c0x00080008
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ror r5, r5, #16 ; [i2 | i3]
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qadd16 r6, r4, r5 ; [i1+i2 | i0+i3] = [b1 | a1] without shift
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qsub16 r7, r4, r5 ; [i1-i2 | i0-i3] = [c1 | d1] without shift
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add r0, r0, r2 ; update input pointer
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qadd16 r7, r7, r7 ; 2*[c1|d1] --> we can use smlad and smlsd
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; with 2217*4 and 5352*4 without losing the
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; sign bit (overflow)
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smuad r4, r6, lr ; o0 = (i1+i2)*8 + (i0+i3)*8
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smusd r5, r6, lr ; o2 = (i1+i2)*8 - (i0+i3)*8
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smlad r6, r7, r12, r11 ; o1 = (c1 * 2217 + d1 * 5352 + 14500)
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smlsdx r7, r7, r12, r10 ; o3 = (d1 * 2217 - c1 * 5352 + 7500)
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ldrd r8, r9, [r0] ; [i5 | i4] [i7 | i6]
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pkhbt r3, r4, r6, lsl #4 ; [o1 | o0], keep in register for PART 2
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pkhbt r6, r5, r7, lsl #4 ; [o3 | o2]
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str r6, [r1, #4]
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; coeffs 4-7
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ror r9, r9, #16 ; [i6 | i7]
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qadd16 r6, r8, r9 ; [i5+i6 | i4+i7] = [b1 | a1] without shift
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qsub16 r7, r8, r9 ; [i5-i6 | i4-i7] = [c1 | d1] without shift
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add r0, r0, r2 ; update input pointer
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qadd16 r7, r7, r7 ; 2x[c1|d1] --> we can use smlad and smlsd
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; with 2217*4 and 5352*4 without losing the
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; sign bit (overflow)
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smuad r9, r6, lr ; o4 = (i5+i6)*8 + (i4+i7)*8
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smusd r8, r6, lr ; o6 = (i5+i6)*8 - (i4+i7)*8
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smlad r6, r7, r12, r11 ; o5 = (c1 * 2217 + d1 * 5352 + 14500)
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smlsdx r7, r7, r12, r10 ; o7 = (d1 * 2217 - c1 * 5352 + 7500)
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ldrd r4, r5, [r0] ; [i9 | i8] [i11 | i10]
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pkhbt r9, r9, r6, lsl #4 ; [o5 | o4], keep in register for PART 2
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pkhbt r6, r8, r7, lsl #4 ; [o7 | o6]
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str r6, [r1, #12]
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; coeffs 8-11
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ror r5, r5, #16 ; [i10 | i11]
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qadd16 r6, r4, r5 ; [i9+i10 | i8+i11]=[b1 | a1] without shift
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qsub16 r7, r4, r5 ; [i9-i10 | i8-i11]=[c1 | d1] without shift
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add r0, r0, r2 ; update input pointer
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qadd16 r7, r7, r7 ; 2x[c1|d1] --> we can use smlad and smlsd
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; with 2217*4 and 5352*4 without losing the
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; sign bit (overflow)
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smuad r2, r6, lr ; o8 = (i9+i10)*8 + (i8+i11)*8
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smusd r8, r6, lr ; o10 = (i9+i10)*8 - (i8+i11)*8
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smlad r6, r7, r12, r11 ; o9 = (c1 * 2217 + d1 * 5352 + 14500)
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smlsdx r7, r7, r12, r10 ; o11 = (d1 * 2217 - c1 * 5352 + 7500)
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ldrd r4, r5, [r0] ; [i13 | i12] [i15 | i14]
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pkhbt r2, r2, r6, lsl #4 ; [o9 | o8], keep in register for PART 2
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pkhbt r6, r8, r7, lsl #4 ; [o11 | o10]
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str r6, [r1, #20]
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; coeffs 12-15
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ror r5, r5, #16 ; [i14 | i15]
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qadd16 r6, r4, r5 ; [i13+i14 | i12+i15]=[b1|a1] without shift
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qsub16 r7, r4, r5 ; [i13-i14 | i12-i15]=[c1|d1] without shift
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qadd16 r7, r7, r7 ; 2x[c1|d1] --> we can use smlad and smlsd
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; with 2217*4 and 5352*4 without losing the
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; sign bit (overflow)
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smuad r4, r6, lr ; o12 = (i13+i14)*8 + (i12+i15)*8
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smusd r5, r6, lr ; o14 = (i13+i14)*8 - (i12+i15)*8
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smlad r6, r7, r12, r11 ; o13 = (c1 * 2217 + d1 * 5352 + 14500)
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smlsdx r7, r7, r12, r10 ; o15 = (d1 * 2217 - c1 * 5352 + 7500)
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pkhbt r0, r4, r6, lsl #4 ; [o13 | o12], keep in register for PART 2
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pkhbt r6, r5, r7, lsl #4 ; [o15 | o14]
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str r6, [r1, #28]
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; PART 2 -------------------------------------------------
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ldr r11, c12000
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ldr r10, c51000
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ldr lr, c0x00070007
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qadd16 r4, r3, r0 ; a1 = [i1+i13 | i0+i12]
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qadd16 r5, r9, r2 ; b1 = [i5+i9 | i4+i8]
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qsub16 r6, r9, r2 ; c1 = [i5-i9 | i4-i8]
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qsub16 r7, r3, r0 ; d1 = [i1-i13 | i0-i12]
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qadd16 r4, r4, lr ; a1 + 7
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add r0, r11, #0x10000 ; add (d!=0)
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qadd16 r2, r4, r5 ; a1 + b1 + 7
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qsub16 r3, r4, r5 ; a1 - b1 + 7
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ldr r12, c0x08a914e8 ; [2217 | 5352]
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lsl r8, r2, #16 ; prepare bottom halfword for scaling
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asr r2, r2, #4 ; scale top halfword
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lsl r9, r3, #16 ; prepare bottom halfword for scaling
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asr r3, r3, #4 ; scale top halfword
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pkhtb r4, r2, r8, asr #20 ; pack and scale bottom halfword
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pkhtb r5, r3, r9, asr #20 ; pack and scale bottom halfword
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smulbt r2, r6, r12 ; [ ------ | c1*2217]
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str r4, [r1, #0] ; [ o1 | o0]
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smultt r3, r6, r12 ; [c1*2217 | ------ ]
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str r5, [r1, #16] ; [ o9 | o8]
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smlabb r8, r7, r12, r2 ; [ ------ | d1*5352]
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smlatb r9, r7, r12, r3 ; [d1*5352 | ------ ]
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smulbb r2, r6, r12 ; [ ------ | c1*5352]
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smultb r3, r6, r12 ; [c1*5352 | ------ ]
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lsls r6, r7, #16 ; d1 != 0 ?
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addeq r8, r8, r11 ; c1_b*2217+d1_b*5352+12000 + (d==0)
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addne r8, r8, r0 ; c1_b*2217+d1_b*5352+12000 + (d!=0)
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asrs r6, r7, #16
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addeq r9, r9, r11 ; c1_t*2217+d1_t*5352+12000 + (d==0)
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addne r9, r9, r0 ; c1_t*2217+d1_t*5352+12000 + (d!=0)
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smlabt r4, r7, r12, r10 ; [ ------ | d1*2217] + 51000
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smlatt r5, r7, r12, r10 ; [d1*2217 | ------ ] + 51000
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pkhtb r9, r9, r8, asr #16
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sub r4, r4, r2
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sub r5, r5, r3
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ldr r3, [r1, #4] ; [i3 | i2]
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pkhtb r5, r5, r4, asr #16 ; [o13|o12]
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str r9, [r1, #8] ; [o5 | 04]
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ldr r9, [r1, #12] ; [i7 | i6]
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ldr r8, [r1, #28] ; [i15|i14]
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ldr r2, [r1, #20] ; [i11|i10]
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str r5, [r1, #24] ; [o13|o12]
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qadd16 r4, r3, r8 ; a1 = [i3+i15 | i2+i14]
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qadd16 r5, r9, r2 ; b1 = [i7+i11 | i6+i10]
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qadd16 r4, r4, lr ; a1 + 7
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qsub16 r6, r9, r2 ; c1 = [i7-i11 | i6-i10]
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qadd16 r2, r4, r5 ; a1 + b1 + 7
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qsub16 r7, r3, r8 ; d1 = [i3-i15 | i2-i14]
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qsub16 r3, r4, r5 ; a1 - b1 + 7
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lsl r8, r2, #16 ; prepare bottom halfword for scaling
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asr r2, r2, #4 ; scale top halfword
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lsl r9, r3, #16 ; prepare bottom halfword for scaling
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asr r3, r3, #4 ; scale top halfword
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pkhtb r4, r2, r8, asr #20 ; pack and scale bottom halfword
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pkhtb r5, r3, r9, asr #20 ; pack and scale bottom halfword
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smulbt r2, r6, r12 ; [ ------ | c1*2217]
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str r4, [r1, #4] ; [ o3 | o2]
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smultt r3, r6, r12 ; [c1*2217 | ------ ]
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str r5, [r1, #20] ; [ o11 | o10]
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smlabb r8, r7, r12, r2 ; [ ------ | d1*5352]
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smlatb r9, r7, r12, r3 ; [d1*5352 | ------ ]
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smulbb r2, r6, r12 ; [ ------ | c1*5352]
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smultb r3, r6, r12 ; [c1*5352 | ------ ]
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lsls r6, r7, #16 ; d1 != 0 ?
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addeq r8, r8, r11 ; c1_b*2217+d1_b*5352+12000 + (d==0)
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addne r8, r8, r0 ; c1_b*2217+d1_b*5352+12000 + (d!=0)
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asrs r6, r7, #16
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addeq r9, r9, r11 ; c1_t*2217+d1_t*5352+12000 + (d==0)
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addne r9, r9, r0 ; c1_t*2217+d1_t*5352+12000 + (d!=0)
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smlabt r4, r7, r12, r10 ; [ ------ | d1*2217] + 51000
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smlatt r5, r7, r12, r10 ; [d1*2217 | ------ ] + 51000
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pkhtb r9, r9, r8, asr #16
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sub r4, r4, r2
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sub r5, r5, r3
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str r9, [r1, #12] ; [o7 | o6]
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pkhtb r5, r5, r4, asr #16 ; [o15|o14]
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str r5, [r1, #28] ; [o15|o14]
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ldmfd sp!, {r4 - r12, pc}
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ENDP
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; Used constants
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c7500
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DCD 7500
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c14500
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DCD 14500
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c0x22a453a0
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DCD 0x22a453a0
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c0x00080008
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DCD 0x00080008
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c12000
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DCD 12000
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c51000
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DCD 51000
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c0x00070007
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DCD 0x00070007
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c0x08a914e8
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DCD 0x08a914e8
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END
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24
vp8/encoder/arm/dct_arm.c
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24
vp8/encoder/arm/dct_arm.c
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@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2011 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include "vpx_config.h"
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#include "vp8/encoder/dct.h"
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#if HAVE_ARMV6
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void vp8_fast_fdct8x4_armv6(short *input, short *output, int pitch)
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{
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vp8_fast_fdct4x4_armv6(input, output, pitch);
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vp8_fast_fdct4x4_armv6(input + 4, output + 16, pitch);
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}
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#endif /* HAVE_ARMV6 */
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@ -14,12 +14,21 @@
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#if HAVE_ARMV6
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extern prototype_fdct(vp8_short_walsh4x4_armv6);
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extern prototype_fdct(vp8_fast_fdct4x4_armv6);
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extern prototype_fdct(vp8_fast_fdct8x4_armv6);
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#if !CONFIG_RUNTIME_CPU_DETECT
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#undef vp8_fdct_walsh_short4x4
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#define vp8_fdct_walsh_short4x4 vp8_short_walsh4x4_armv6
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#undef vp8_fdct_fast4x4
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#define vp8_fdct_fast4x4 vp8_fast_fdct4x4_armv6
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#undef vp8_fdct_fast8x4
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#define vp8_fdct_fast8x4 vp8_fast_fdct8x4_armv6
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#endif
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#endif
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#endif /* HAVE_ARMV6 */
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#if HAVE_ARMV7
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extern prototype_fdct(vp8_short_fdct4x4_neon);
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@ -19,6 +19,7 @@ VP8_CX_SRCS-$(ARCH_ARM) += encoder/asm_enc_offsets.c
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VP8_CX_SRCS-$(HAVE_ARMV7) += encoder/arm/encodemb_arm.c
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VP8_CX_SRCS-$(HAVE_ARMV7) += encoder/arm/quantize_arm.c
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VP8_CX_SRCS-$(HAVE_ARMV7) += encoder/arm/picklpf_arm.c
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VP8_CX_SRCS-$(HAVE_ARMV6) += encoder/arm/dct_arm.c
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VP8_CX_SRCS-$(HAVE_ARMV6) += encoder/arm/variance_arm.c
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VP8_CX_SRCS-$(HAVE_ARMV6) += encoder/arm/variance_arm.h
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VP8_CX_SRCS-$(HAVE_ARMV5TE) += encoder/arm/boolhuff_arm.c
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@ -34,6 +35,7 @@ VP8_CX_SRCS-$(HAVE_ARMV5TE) += encoder/arm/armv5te/vp8_packtokens_partitions_ar
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#File list for armv6
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# encoder
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VP8_CX_SRCS-$(HAVE_ARMV6) += encoder/arm/armv6/vp8_fast_fdct4x4_armv6$(ASM)
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VP8_CX_SRCS-$(HAVE_ARMV6) += encoder/arm/armv6/vp8_fast_quantize_b_armv6$(ASM)
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VP8_CX_SRCS-$(HAVE_ARMV6) += encoder/arm/armv6/vp8_sad16x16_armv6$(ASM)
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VP8_CX_SRCS-$(HAVE_ARMV6) += encoder/arm/armv6/vp8_variance16x16_armv6$(ASM)
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