partial fdct neon: add 32x32_1
Always return an int32_t. Since it needs to be moved to a register for shifting, this doesn't really penalize the smaller transforms. The values could potentially be summed and shifted in place. BUG=webm:1424 Change-Id: Id5beb35d79c7574ebd99285fc4182788cf2bb972
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@ -142,7 +142,8 @@ INSTANTIATE_TEST_CASE_P(
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#if CONFIG_VP9_HIGHBITDEPTH
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INSTANTIATE_TEST_CASE_P(
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NEON, PartialFdctTest,
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::testing::Values(make_tuple(&vpx_fdct16x16_1_neon, 16, VPX_BITS_8),
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::testing::Values(make_tuple(&vpx_fdct32x32_1_neon, 32, VPX_BITS_8),
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make_tuple(&vpx_fdct16x16_1_neon, 16, VPX_BITS_8),
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make_tuple(&vpx_fdct8x8_1_neon, 8, VPX_BITS_12),
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make_tuple(&vpx_fdct8x8_1_neon, 8, VPX_BITS_10),
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make_tuple(&vpx_fdct8x8_1_neon, 8, VPX_BITS_8),
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@ -150,7 +151,8 @@ INSTANTIATE_TEST_CASE_P(
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#else
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INSTANTIATE_TEST_CASE_P(
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NEON, PartialFdctTest,
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::testing::Values(make_tuple(&vpx_fdct16x16_1_neon, 16, VPX_BITS_8),
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::testing::Values(make_tuple(&vpx_fdct32x32_1_neon, 32, VPX_BITS_8),
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make_tuple(&vpx_fdct16x16_1_neon, 16, VPX_BITS_8),
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make_tuple(&vpx_fdct8x8_1_neon, 8, VPX_BITS_8),
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make_tuple(&vpx_fdct4x4_1_neon, 4, VPX_BITS_8)));
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#endif // CONFIG_VP9_HIGHBITDEPTH
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@ -14,16 +14,12 @@
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#include "./vpx_config.h"
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#include "vpx_dsp/arm/mem_neon.h"
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static INLINE tran_low_t sum_int16x8(const int16x8_t a) {
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static INLINE int32_t sum_int16x8(const int16x8_t a) {
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const int32x4_t b = vpaddlq_s16(a);
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const int64x2_t c = vpaddlq_s32(b);
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const int32x2_t d = vadd_s32(vreinterpret_s32_s64(vget_low_s64(c)),
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vreinterpret_s32_s64(vget_high_s64(c)));
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#if CONFIG_VP9_HIGHBITDEPTH
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return vget_lane_s32(d, 0);
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#else
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return vget_lane_s16(vreinterpret_s16_s32(d), 0);
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#endif
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}
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void vpx_fdct4x4_1_neon(const int16_t *input, tran_low_t *output, int stride) {
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@ -44,7 +40,7 @@ void vpx_fdct4x4_1_neon(const int16_t *input, tran_low_t *output, int stride) {
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c = vaddq_s16(b0, b1);
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output[0] = sum_int16x8(c) << 1;
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output[0] = (tran_low_t)(sum_int16x8(c) << 1);
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output[1] = 0;
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}
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@ -56,7 +52,7 @@ void vpx_fdct8x8_1_neon(const int16_t *input, tran_low_t *output, int stride) {
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sum = vaddq_s16(sum, input_00);
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}
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output[0] = sum_int16x8(sum);
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output[0] = (tran_low_t)sum_int16x8(sum);
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output[1] = 0;
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}
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@ -74,6 +70,33 @@ void vpx_fdct16x16_1_neon(const int16_t *input, tran_low_t *output,
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right = vaddq_s16(right, b);
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}
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output[0] = (sum_int16x8(left) + sum_int16x8(right)) >> 1;
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output[0] = (tran_low_t)((sum_int16x8(left) + sum_int16x8(right)) >> 1);
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output[1] = 0;
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}
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void vpx_fdct32x32_1_neon(const int16_t *input, tran_low_t *output,
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int stride) {
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int r;
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int16x8_t a0 = vld1q_s16(input);
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int16x8_t a1 = vld1q_s16(input + 8);
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int16x8_t a2 = vld1q_s16(input + 16);
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int16x8_t a3 = vld1q_s16(input + 24);
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input += stride;
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for (r = 1; r < 32; ++r) {
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const int16x8_t b0 = vld1q_s16(input);
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const int16x8_t b1 = vld1q_s16(input + 8);
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const int16x8_t b2 = vld1q_s16(input + 16);
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const int16x8_t b3 = vld1q_s16(input + 24);
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input += stride;
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a0 = vaddq_s16(a0, b0);
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a1 = vaddq_s16(a1, b1);
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a2 = vaddq_s16(a2, b2);
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a3 = vaddq_s16(a3, b3);
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}
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// TODO(johannkoenig): sum and shift the values in neon registers.
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output[0] = (tran_low_t)(
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(sum_int16x8(a0) + sum_int16x8(a1) + sum_int16x8(a2) + sum_int16x8(a3)) >>
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3);
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output[1] = 0;
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}
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@ -508,7 +508,7 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
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specialize qw/vpx_fdct32x32_rd sse2/;
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add_proto qw/void vpx_fdct32x32_1/, "const int16_t *input, tran_low_t *output, int stride";
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specialize qw/vpx_fdct32x32_1 sse2/;
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specialize qw/vpx_fdct32x32_1 sse2 neon/;
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add_proto qw/void vpx_highbd_fdct4x4/, "const int16_t *input, tran_low_t *output, int stride";
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specialize qw/vpx_highbd_fdct4x4 sse2/;
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@ -558,7 +558,7 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
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specialize qw/vpx_fdct32x32_rd sse2 avx2 msa/;
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add_proto qw/void vpx_fdct32x32_1/, "const int16_t *input, tran_low_t *output, int stride";
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specialize qw/vpx_fdct32x32_1 sse2 msa/;
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specialize qw/vpx_fdct32x32_1 sse2 neon msa/;
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} # CONFIG_VP9_HIGHBITDEPTH
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} # CONFIG_VP9_ENCODER
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