Add vp9_highbd_iht16x16_256_add_neon()
BUG=webm:1403 Change-Id: I2293c11666786be276909d48ee78dacb40a89e25
This commit is contained in:
Linfeng Zhang
parent
d8424d2890
commit
9351f96069
@ -401,8 +401,7 @@ class TransTestBase : public ::testing::TestWithParam<DctParam> {
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EXPECT_GE(static_cast<uint32_t>(limit), error)
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<< "Error: " << size_ << "x" << size_
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<< " inverse transform has error " << error << " at " << w << ","
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<< h << " org:" << (int)src_[h * stride_ + w]
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<< " opt:" << (int)dst_[h * stride_ + w];
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<< h;
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if (::testing::Test::HasFailure()) {
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printf("Size: %d Transform type: %d\n", size_, tx_type_);
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return;
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@ -633,6 +632,8 @@ static const FuncInfo ht_neon_func_info[] = {
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2 },
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{ &vp9_highbd_fht8x8_c, &highbd_iht_wrapper<vp9_highbd_iht8x8_64_add_neon>, 8,
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2 },
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{ &vp9_highbd_fht16x16_c,
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&highbd_iht_wrapper<vp9_highbd_iht16x16_256_add_neon>, 16, 2 },
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#endif
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{ &vp9_fht4x4_c, &iht_wrapper<vp9_iht4x4_16_add_neon>, 4, 1 },
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{ &vp9_fht8x8_c, &iht_wrapper<vp9_iht8x8_64_add_neon>, 8, 1 },
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445
vp9/common/arm/neon/vp9_highbd_iht16x16_add_neon.c
Normal file
445
vp9/common/arm/neon/vp9_highbd_iht16x16_add_neon.c
Normal file
@ -0,0 +1,445 @@
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/*
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* Copyright (c) 2018 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <arm_neon.h>
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#include "./vpx_dsp_rtcd.h"
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#include "vp9/common/vp9_enums.h"
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#include "vp9/common/arm/neon/vp9_iht_neon.h"
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#include "vpx_dsp/arm/highbd_idct_neon.h"
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#include "vpx_dsp/arm/idct_neon.h"
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#include "vpx_dsp/arm/transpose_neon.h"
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#include "vpx_dsp/inv_txfm.h"
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// Use macros to make sure argument lane is passed in as an constant integer.
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#define vmull_lane_s32_dual(in, c, lane, out) \
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do { \
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out[0].val[0] = vmull_lane_s32(vget_low_s32(in.val[0]), c, lane); \
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out[0].val[1] = vmull_lane_s32(vget_low_s32(in.val[1]), c, lane); \
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out[1].val[0] = vmull_lane_s32(vget_high_s32(in.val[0]), c, lane); \
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out[1].val[1] = vmull_lane_s32(vget_high_s32(in.val[1]), c, lane); \
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} while (0)
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#define vmlal_lane_s32_dual(in, c, lane, out) \
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do { \
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out[0].val[0] = \
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vmlal_lane_s32(out[0].val[0], vget_low_s32(in.val[0]), c, lane); \
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out[0].val[1] = \
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vmlal_lane_s32(out[0].val[1], vget_low_s32(in.val[1]), c, lane); \
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out[1].val[0] = \
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vmlal_lane_s32(out[1].val[0], vget_high_s32(in.val[0]), c, lane); \
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out[1].val[1] = \
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vmlal_lane_s32(out[1].val[1], vget_high_s32(in.val[1]), c, lane); \
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} while (0)
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#define vmlsl_lane_s32_dual(in, c, lane, out) \
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do { \
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out[0].val[0] = \
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vmlsl_lane_s32(out[0].val[0], vget_low_s32(in.val[0]), c, lane); \
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out[0].val[1] = \
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vmlsl_lane_s32(out[0].val[1], vget_low_s32(in.val[1]), c, lane); \
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out[1].val[0] = \
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vmlsl_lane_s32(out[1].val[0], vget_high_s32(in.val[0]), c, lane); \
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out[1].val[1] = \
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vmlsl_lane_s32(out[1].val[1], vget_high_s32(in.val[1]), c, lane); \
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} while (0)
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static INLINE int32x4x2_t
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highbd_dct_const_round_shift_low_8(const int64x2x2_t *const in) {
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int32x4x2_t out;
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out.val[0] = vcombine_s32(vrshrn_n_s64(in[0].val[0], DCT_CONST_BITS),
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vrshrn_n_s64(in[1].val[0], DCT_CONST_BITS));
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out.val[1] = vcombine_s32(vrshrn_n_s64(in[0].val[1], DCT_CONST_BITS),
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vrshrn_n_s64(in[1].val[1], DCT_CONST_BITS));
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return out;
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}
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#define highbd_iadst_half_butterfly(in, c, lane, out) \
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do { \
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int64x2x2_t t[2]; \
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vmull_lane_s32_dual(in, c, lane, t); \
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out = highbd_dct_const_round_shift_low_8(t); \
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} while (0)
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#define highbd_iadst_butterfly(in0, in1, c, lane0, lane1, s0, s1) \
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do { \
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vmull_lane_s32_dual(in0, c, lane0, s0); \
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vmull_lane_s32_dual(in0, c, lane1, s1); \
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vmlal_lane_s32_dual(in1, c, lane1, s0); \
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vmlsl_lane_s32_dual(in1, c, lane0, s1); \
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} while (0)
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static INLINE int32x4x2_t vaddq_s32_dual(const int32x4x2_t in0,
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const int32x4x2_t in1) {
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int32x4x2_t out;
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out.val[0] = vaddq_s32(in0.val[0], in1.val[0]);
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out.val[1] = vaddq_s32(in0.val[1], in1.val[1]);
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return out;
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}
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static INLINE int64x2x2_t vaddq_s64_dual(const int64x2x2_t in0,
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const int64x2x2_t in1) {
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int64x2x2_t out;
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out.val[0] = vaddq_s64(in0.val[0], in1.val[0]);
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out.val[1] = vaddq_s64(in0.val[1], in1.val[1]);
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return out;
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}
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static INLINE int32x4x2_t vsubq_s32_dual(const int32x4x2_t in0,
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const int32x4x2_t in1) {
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int32x4x2_t out;
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out.val[0] = vsubq_s32(in0.val[0], in1.val[0]);
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out.val[1] = vsubq_s32(in0.val[1], in1.val[1]);
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return out;
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}
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static INLINE int64x2x2_t vsubq_s64_dual(const int64x2x2_t in0,
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const int64x2x2_t in1) {
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int64x2x2_t out;
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out.val[0] = vsubq_s64(in0.val[0], in1.val[0]);
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out.val[1] = vsubq_s64(in0.val[1], in1.val[1]);
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return out;
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}
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static INLINE int32x4x2_t vcombine_s32_dual(const int32x2x2_t in0,
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const int32x2x2_t in1) {
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int32x4x2_t out;
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out.val[0] = vcombine_s32(in0.val[0], in1.val[0]);
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out.val[1] = vcombine_s32(in0.val[1], in1.val[1]);
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return out;
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}
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static INLINE int32x4x2_t highbd_add_dct_const_round_shift_low_8(
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const int64x2x2_t *const in0, const int64x2x2_t *const in1) {
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const int64x2x2_t sum_lo = vaddq_s64_dual(in0[0], in1[0]);
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const int64x2x2_t sum_hi = vaddq_s64_dual(in0[1], in1[1]);
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int32x2x2_t out_lo, out_hi;
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out_lo.val[0] = vrshrn_n_s64(sum_lo.val[0], DCT_CONST_BITS);
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out_lo.val[1] = vrshrn_n_s64(sum_lo.val[1], DCT_CONST_BITS);
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out_hi.val[0] = vrshrn_n_s64(sum_hi.val[0], DCT_CONST_BITS);
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out_hi.val[1] = vrshrn_n_s64(sum_hi.val[1], DCT_CONST_BITS);
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return vcombine_s32_dual(out_lo, out_hi);
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}
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static INLINE int32x4x2_t highbd_sub_dct_const_round_shift_low_8(
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const int64x2x2_t *const in0, const int64x2x2_t *const in1) {
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const int64x2x2_t sub_lo = vsubq_s64_dual(in0[0], in1[0]);
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const int64x2x2_t sub_hi = vsubq_s64_dual(in0[1], in1[1]);
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int32x2x2_t out_lo, out_hi;
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out_lo.val[0] = vrshrn_n_s64(sub_lo.val[0], DCT_CONST_BITS);
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out_lo.val[1] = vrshrn_n_s64(sub_lo.val[1], DCT_CONST_BITS);
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out_hi.val[0] = vrshrn_n_s64(sub_hi.val[0], DCT_CONST_BITS);
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out_hi.val[1] = vrshrn_n_s64(sub_hi.val[1], DCT_CONST_BITS);
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return vcombine_s32_dual(out_lo, out_hi);
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}
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static INLINE int32x4x2_t vnegq_s32_dual(const int32x4x2_t in) {
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int32x4x2_t out;
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out.val[0] = vnegq_s32(in.val[0]);
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out.val[1] = vnegq_s32(in.val[1]);
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return out;
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}
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void vpx_highbd_iadst16_neon(const int32_t *input, int32_t *output,
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uint16_t *dest, const int stride, const int bd) {
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const int32x4_t c_1_31_5_27 =
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create_s32x4_neon(cospi_1_64, cospi_31_64, cospi_5_64, cospi_27_64);
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const int32x4_t c_9_23_13_19 =
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create_s32x4_neon(cospi_9_64, cospi_23_64, cospi_13_64, cospi_19_64);
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const int32x4_t c_17_15_21_11 =
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create_s32x4_neon(cospi_17_64, cospi_15_64, cospi_21_64, cospi_11_64);
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const int32x4_t c_25_7_29_3 =
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create_s32x4_neon(cospi_25_64, cospi_7_64, cospi_29_64, cospi_3_64);
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const int32x4_t c_4_28_20_12 =
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create_s32x4_neon(cospi_4_64, cospi_28_64, cospi_20_64, cospi_12_64);
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const int32x4_t c_16_n16_8_24 =
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create_s32x4_neon(cospi_16_64, -cospi_16_64, cospi_8_64, cospi_24_64);
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int32x4x2_t in[16], out[16];
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int32x4x2_t x[16], t[12];
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int64x2x2_t s0[2], s1[2], s2[2], s3[2], s4[2], s5[2], s6[2], s7[2];
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int64x2x2_t s8[2], s9[2], s10[2], s11[2], s12[2], s13[2], s14[2], s15[2];
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// Load input (16x8)
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in[0].val[0] = vld1q_s32(input);
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in[0].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[8].val[0] = vld1q_s32(input);
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in[8].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[1].val[0] = vld1q_s32(input);
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in[1].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[9].val[0] = vld1q_s32(input);
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in[9].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[2].val[0] = vld1q_s32(input);
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in[2].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[10].val[0] = vld1q_s32(input);
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in[10].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[3].val[0] = vld1q_s32(input);
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in[3].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[11].val[0] = vld1q_s32(input);
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in[11].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[4].val[0] = vld1q_s32(input);
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in[4].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[12].val[0] = vld1q_s32(input);
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in[12].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[5].val[0] = vld1q_s32(input);
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in[5].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[13].val[0] = vld1q_s32(input);
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in[13].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[6].val[0] = vld1q_s32(input);
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in[6].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[14].val[0] = vld1q_s32(input);
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in[14].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[7].val[0] = vld1q_s32(input);
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in[7].val[1] = vld1q_s32(input + 4);
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input += 8;
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in[15].val[0] = vld1q_s32(input);
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in[15].val[1] = vld1q_s32(input + 4);
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// Transpose
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transpose_s32_8x8(&in[0], &in[1], &in[2], &in[3], &in[4], &in[5], &in[6],
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&in[7]);
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transpose_s32_8x8(&in[8], &in[9], &in[10], &in[11], &in[12], &in[13], &in[14],
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&in[15]);
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x[0] = in[15];
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x[1] = in[0];
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x[2] = in[13];
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x[3] = in[2];
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x[4] = in[11];
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x[5] = in[4];
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x[6] = in[9];
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x[7] = in[6];
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x[8] = in[7];
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x[9] = in[8];
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x[10] = in[5];
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x[11] = in[10];
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x[12] = in[3];
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x[13] = in[12];
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x[14] = in[1];
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x[15] = in[14];
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// stage 1
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highbd_iadst_butterfly(x[0], x[1], vget_low_s32(c_1_31_5_27), 0, 1, s0, s1);
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highbd_iadst_butterfly(x[2], x[3], vget_high_s32(c_1_31_5_27), 0, 1, s2, s3);
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highbd_iadst_butterfly(x[4], x[5], vget_low_s32(c_9_23_13_19), 0, 1, s4, s5);
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highbd_iadst_butterfly(x[6], x[7], vget_high_s32(c_9_23_13_19), 0, 1, s6, s7);
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highbd_iadst_butterfly(x[8], x[9], vget_low_s32(c_17_15_21_11), 0, 1, s8, s9);
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highbd_iadst_butterfly(x[10], x[11], vget_high_s32(c_17_15_21_11), 0, 1, s10,
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s11);
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highbd_iadst_butterfly(x[12], x[13], vget_low_s32(c_25_7_29_3), 0, 1, s12,
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s13);
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highbd_iadst_butterfly(x[14], x[15], vget_high_s32(c_25_7_29_3), 0, 1, s14,
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s15);
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x[0] = highbd_add_dct_const_round_shift_low_8(s0, s8);
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x[1] = highbd_add_dct_const_round_shift_low_8(s1, s9);
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x[2] = highbd_add_dct_const_round_shift_low_8(s2, s10);
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x[3] = highbd_add_dct_const_round_shift_low_8(s3, s11);
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x[4] = highbd_add_dct_const_round_shift_low_8(s4, s12);
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x[5] = highbd_add_dct_const_round_shift_low_8(s5, s13);
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x[6] = highbd_add_dct_const_round_shift_low_8(s6, s14);
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x[7] = highbd_add_dct_const_round_shift_low_8(s7, s15);
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x[8] = highbd_sub_dct_const_round_shift_low_8(s0, s8);
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x[9] = highbd_sub_dct_const_round_shift_low_8(s1, s9);
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x[10] = highbd_sub_dct_const_round_shift_low_8(s2, s10);
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x[11] = highbd_sub_dct_const_round_shift_low_8(s3, s11);
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x[12] = highbd_sub_dct_const_round_shift_low_8(s4, s12);
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x[13] = highbd_sub_dct_const_round_shift_low_8(s5, s13);
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x[14] = highbd_sub_dct_const_round_shift_low_8(s6, s14);
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x[15] = highbd_sub_dct_const_round_shift_low_8(s7, s15);
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// stage 2
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t[0] = x[0];
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t[1] = x[1];
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t[2] = x[2];
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t[3] = x[3];
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t[4] = x[4];
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t[5] = x[5];
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t[6] = x[6];
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t[7] = x[7];
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highbd_iadst_butterfly(x[8], x[9], vget_low_s32(c_4_28_20_12), 0, 1, s8, s9);
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highbd_iadst_butterfly(x[10], x[11], vget_high_s32(c_4_28_20_12), 0, 1, s10,
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s11);
|
||||
highbd_iadst_butterfly(x[13], x[12], vget_low_s32(c_4_28_20_12), 1, 0, s13,
|
||||
s12);
|
||||
highbd_iadst_butterfly(x[15], x[14], vget_high_s32(c_4_28_20_12), 1, 0, s15,
|
||||
s14);
|
||||
|
||||
x[0] = vaddq_s32_dual(t[0], t[4]);
|
||||
x[1] = vaddq_s32_dual(t[1], t[5]);
|
||||
x[2] = vaddq_s32_dual(t[2], t[6]);
|
||||
x[3] = vaddq_s32_dual(t[3], t[7]);
|
||||
x[4] = vsubq_s32_dual(t[0], t[4]);
|
||||
x[5] = vsubq_s32_dual(t[1], t[5]);
|
||||
x[6] = vsubq_s32_dual(t[2], t[6]);
|
||||
x[7] = vsubq_s32_dual(t[3], t[7]);
|
||||
x[8] = highbd_add_dct_const_round_shift_low_8(s8, s12);
|
||||
x[9] = highbd_add_dct_const_round_shift_low_8(s9, s13);
|
||||
x[10] = highbd_add_dct_const_round_shift_low_8(s10, s14);
|
||||
x[11] = highbd_add_dct_const_round_shift_low_8(s11, s15);
|
||||
x[12] = highbd_sub_dct_const_round_shift_low_8(s8, s12);
|
||||
x[13] = highbd_sub_dct_const_round_shift_low_8(s9, s13);
|
||||
x[14] = highbd_sub_dct_const_round_shift_low_8(s10, s14);
|
||||
x[15] = highbd_sub_dct_const_round_shift_low_8(s11, s15);
|
||||
|
||||
// stage 3
|
||||
t[0] = x[0];
|
||||
t[1] = x[1];
|
||||
t[2] = x[2];
|
||||
t[3] = x[3];
|
||||
highbd_iadst_butterfly(x[4], x[5], vget_high_s32(c_16_n16_8_24), 0, 1, s4,
|
||||
s5);
|
||||
highbd_iadst_butterfly(x[7], x[6], vget_high_s32(c_16_n16_8_24), 1, 0, s7,
|
||||
s6);
|
||||
t[8] = x[8];
|
||||
t[9] = x[9];
|
||||
t[10] = x[10];
|
||||
t[11] = x[11];
|
||||
highbd_iadst_butterfly(x[12], x[13], vget_high_s32(c_16_n16_8_24), 0, 1, s12,
|
||||
s13);
|
||||
highbd_iadst_butterfly(x[15], x[14], vget_high_s32(c_16_n16_8_24), 1, 0, s15,
|
||||
s14);
|
||||
|
||||
x[0] = vaddq_s32_dual(t[0], t[2]);
|
||||
x[1] = vaddq_s32_dual(t[1], t[3]);
|
||||
x[2] = vsubq_s32_dual(t[0], t[2]);
|
||||
x[3] = vsubq_s32_dual(t[1], t[3]);
|
||||
x[4] = highbd_add_dct_const_round_shift_low_8(s4, s6);
|
||||
x[5] = highbd_add_dct_const_round_shift_low_8(s5, s7);
|
||||
x[6] = highbd_sub_dct_const_round_shift_low_8(s4, s6);
|
||||
x[7] = highbd_sub_dct_const_round_shift_low_8(s5, s7);
|
||||
x[8] = vaddq_s32_dual(t[8], t[10]);
|
||||
x[9] = vaddq_s32_dual(t[9], t[11]);
|
||||
x[10] = vsubq_s32_dual(t[8], t[10]);
|
||||
x[11] = vsubq_s32_dual(t[9], t[11]);
|
||||
x[12] = highbd_add_dct_const_round_shift_low_8(s12, s14);
|
||||
x[13] = highbd_add_dct_const_round_shift_low_8(s13, s15);
|
||||
x[14] = highbd_sub_dct_const_round_shift_low_8(s12, s14);
|
||||
x[15] = highbd_sub_dct_const_round_shift_low_8(s13, s15);
|
||||
|
||||
// stage 4
|
||||
{
|
||||
const int32x4x2_t sum = vaddq_s32_dual(x[2], x[3]);
|
||||
const int32x4x2_t sub = vsubq_s32_dual(x[2], x[3]);
|
||||
highbd_iadst_half_butterfly(sum, vget_low_s32(c_16_n16_8_24), 1, x[2]);
|
||||
highbd_iadst_half_butterfly(sub, vget_low_s32(c_16_n16_8_24), 0, x[3]);
|
||||
}
|
||||
{
|
||||
const int32x4x2_t sum = vaddq_s32_dual(x[7], x[6]);
|
||||
const int32x4x2_t sub = vsubq_s32_dual(x[7], x[6]);
|
||||
highbd_iadst_half_butterfly(sum, vget_low_s32(c_16_n16_8_24), 0, x[6]);
|
||||
highbd_iadst_half_butterfly(sub, vget_low_s32(c_16_n16_8_24), 0, x[7]);
|
||||
}
|
||||
{
|
||||
const int32x4x2_t sum = vaddq_s32_dual(x[11], x[10]);
|
||||
const int32x4x2_t sub = vsubq_s32_dual(x[11], x[10]);
|
||||
highbd_iadst_half_butterfly(sum, vget_low_s32(c_16_n16_8_24), 0, x[10]);
|
||||
highbd_iadst_half_butterfly(sub, vget_low_s32(c_16_n16_8_24), 0, x[11]);
|
||||
}
|
||||
{
|
||||
const int32x4x2_t sum = vaddq_s32_dual(x[14], x[15]);
|
||||
const int32x4x2_t sub = vsubq_s32_dual(x[14], x[15]);
|
||||
highbd_iadst_half_butterfly(sum, vget_low_s32(c_16_n16_8_24), 1, x[14]);
|
||||
highbd_iadst_half_butterfly(sub, vget_low_s32(c_16_n16_8_24), 0, x[15]);
|
||||
}
|
||||
|
||||
out[0] = x[0];
|
||||
out[1] = vnegq_s32_dual(x[8]);
|
||||
out[2] = x[12];
|
||||
out[3] = vnegq_s32_dual(x[4]);
|
||||
out[4] = x[6];
|
||||
out[5] = x[14];
|
||||
out[6] = x[10];
|
||||
out[7] = x[2];
|
||||
out[8] = x[3];
|
||||
out[9] = x[11];
|
||||
out[10] = x[15];
|
||||
out[11] = x[7];
|
||||
out[12] = x[5];
|
||||
out[13] = vnegq_s32_dual(x[13]);
|
||||
out[14] = x[9];
|
||||
out[15] = vnegq_s32_dual(x[1]);
|
||||
|
||||
if (output) {
|
||||
highbd_idct16x16_store_pass1(out, output);
|
||||
} else {
|
||||
highbd_idct16x16_add_store(out, dest, stride, bd);
|
||||
}
|
||||
}
|
||||
|
||||
typedef void (*highbd_iht_1d)(const int32_t *input, int32_t *output,
|
||||
uint16_t *dest, const int stride, const int bd);
|
||||
|
||||
typedef struct {
|
||||
highbd_iht_1d cols, rows; // vertical and horizontal
|
||||
} highbd_iht_2d;
|
||||
|
||||
void vp9_highbd_iht16x16_256_add_neon(const tran_low_t *input, uint16_t *dest,
|
||||
int stride, int tx_type, int bd) {
|
||||
if (bd == 8) {
|
||||
static const iht_2d IHT_16[] = {
|
||||
{ vpx_idct16x16_256_add_half1d,
|
||||
vpx_idct16x16_256_add_half1d }, // DCT_DCT = 0
|
||||
{ vpx_iadst16x16_256_add_half1d,
|
||||
vpx_idct16x16_256_add_half1d }, // ADST_DCT = 1
|
||||
{ vpx_idct16x16_256_add_half1d,
|
||||
vpx_iadst16x16_256_add_half1d }, // DCT_ADST = 2
|
||||
{ vpx_iadst16x16_256_add_half1d,
|
||||
vpx_iadst16x16_256_add_half1d } // ADST_ADST = 3
|
||||
};
|
||||
const iht_2d ht = IHT_16[tx_type];
|
||||
int16_t row_output[16 * 16];
|
||||
|
||||
// pass 1
|
||||
ht.rows(input, row_output, dest, stride, 1); // upper 8 rows
|
||||
ht.rows(input + 8 * 16, row_output + 8, dest, stride, 1); // lower 8 rows
|
||||
|
||||
// pass 2
|
||||
ht.cols(row_output, NULL, dest, stride, 1); // left 8 columns
|
||||
ht.cols(row_output + 16 * 8, NULL, dest + 8, stride, 1); // right 8 columns
|
||||
} else {
|
||||
static const highbd_iht_2d IHT_16[] = {
|
||||
{ vpx_highbd_idct16x16_256_add_half1d,
|
||||
vpx_highbd_idct16x16_256_add_half1d }, // DCT_DCT = 0
|
||||
{ vpx_highbd_iadst16_neon,
|
||||
vpx_highbd_idct16x16_256_add_half1d }, // ADST_DCT = 1
|
||||
{ vpx_highbd_idct16x16_256_add_half1d,
|
||||
vpx_highbd_iadst16_neon }, // DCT_ADST = 2
|
||||
{ vpx_highbd_iadst16_neon, vpx_highbd_iadst16_neon } // ADST_ADST = 3
|
||||
};
|
||||
const highbd_iht_2d ht = IHT_16[tx_type];
|
||||
int32_t row_output[16 * 16];
|
||||
|
||||
// pass 1
|
||||
ht.rows(input, row_output, dest, stride, bd); // upper 8 rows
|
||||
ht.rows(input + 8 * 16, row_output + 8, dest, stride, bd); // lower 8 rows
|
||||
|
||||
// pass 2
|
||||
ht.cols(row_output, NULL, dest, stride, bd); // left 8 columns
|
||||
ht.cols(row_output + 8 * 16, NULL, dest + 8, stride,
|
||||
bd); // right 8 columns
|
||||
}
|
||||
}
|
||||
@ -19,9 +19,9 @@
|
||||
#include "vpx_dsp/arm/mem_neon.h"
|
||||
#include "vpx_dsp/arm/transpose_neon.h"
|
||||
|
||||
static void iadst16x16_256_add_half1d(const void *const input, int16_t *output,
|
||||
void *const dest, const int stride,
|
||||
const int highbd_flag) {
|
||||
void vpx_iadst16x16_256_add_half1d(const void *const input, int16_t *output,
|
||||
void *const dest, const int stride,
|
||||
const int highbd_flag) {
|
||||
int16x8_t in[16], out[16];
|
||||
const int16x4_t c_1_31_5_27 =
|
||||
create_s16x4_neon(cospi_1_64, cospi_31_64, cospi_5_64, cospi_27_64);
|
||||
@ -254,24 +254,17 @@ static void iadst16x16_256_add_half1d(const void *const input, int16_t *output,
|
||||
}
|
||||
}
|
||||
|
||||
typedef void (*iht_1d)(const void *const input, int16_t *output,
|
||||
void *const dest, const int stride,
|
||||
const int highbd_flag);
|
||||
|
||||
typedef struct {
|
||||
iht_1d cols, rows; // vertical and horizontal
|
||||
} iht_2d;
|
||||
|
||||
void vp9_iht16x16_256_add_neon(const tran_low_t *input, uint8_t *dest,
|
||||
int stride, int tx_type) {
|
||||
static const iht_2d IHT_16[] = {
|
||||
{ vpx_idct16x16_256_add_half1d,
|
||||
vpx_idct16x16_256_add_half1d }, // DCT_DCT = 0
|
||||
{ iadst16x16_256_add_half1d,
|
||||
{ vpx_iadst16x16_256_add_half1d,
|
||||
vpx_idct16x16_256_add_half1d }, // ADST_DCT = 1
|
||||
{ vpx_idct16x16_256_add_half1d,
|
||||
iadst16x16_256_add_half1d }, // DCT_ADST = 2
|
||||
{ iadst16x16_256_add_half1d, iadst16x16_256_add_half1d } // ADST_ADST = 3
|
||||
vpx_iadst16x16_256_add_half1d }, // DCT_ADST = 2
|
||||
{ vpx_iadst16x16_256_add_half1d,
|
||||
vpx_iadst16x16_256_add_half1d } // ADST_ADST = 3
|
||||
};
|
||||
const iht_2d ht = IHT_16[tx_type];
|
||||
int16_t row_output[16 * 16];
|
||||
|
||||
@ -257,4 +257,16 @@ static INLINE void iadst8(int16x8_t *const io) {
|
||||
io[7] = vnegq_s16(x[1]);
|
||||
}
|
||||
|
||||
void vpx_iadst16x16_256_add_half1d(const void *const input, int16_t *output,
|
||||
void *const dest, const int stride,
|
||||
const int highbd_flag);
|
||||
|
||||
typedef void (*iht_1d)(const void *const input, int16_t *output,
|
||||
void *const dest, const int stride,
|
||||
const int highbd_flag);
|
||||
|
||||
typedef struct {
|
||||
iht_1d cols, rows; // vertical and horizontal
|
||||
} iht_2d;
|
||||
|
||||
#endif // VP9_COMMON_ARM_NEON_VP9_IHT_NEON_H_
|
||||
|
||||
@ -105,7 +105,7 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
|
||||
if (vpx_config("CONFIG_EMULATE_HARDWARE") ne "yes") {
|
||||
specialize qw/vp9_highbd_iht4x4_16_add neon sse4_1/;
|
||||
specialize qw/vp9_highbd_iht8x8_64_add neon sse4_1/;
|
||||
specialize qw/vp9_highbd_iht16x16_256_add sse4_1/;
|
||||
specialize qw/vp9_highbd_iht16x16_256_add neon sse4_1/;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -85,6 +85,7 @@ VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_itrans16_dspr2.c
|
||||
else
|
||||
VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_highbd_iht4x4_add_neon.c
|
||||
VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_highbd_iht8x8_add_neon.c
|
||||
VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_highbd_iht16x16_add_neon.c
|
||||
VP9_COMMON_SRCS-$(HAVE_SSE4_1) += common/x86/vp9_highbd_iht4x4_add_sse4.c
|
||||
VP9_COMMON_SRCS-$(HAVE_SSE4_1) += common/x86/vp9_highbd_iht8x8_add_sse4.c
|
||||
VP9_COMMON_SRCS-$(HAVE_SSE4_1) += common/x86/vp9_highbd_iht16x16_add_sse4.c
|
||||
|
||||
@ -11,6 +11,7 @@
|
||||
#include <arm_neon.h>
|
||||
|
||||
#include "./vpx_dsp_rtcd.h"
|
||||
#include "vpx_dsp/arm/highbd_idct_neon.h"
|
||||
#include "vpx_dsp/arm/idct_neon.h"
|
||||
#include "vpx_dsp/inv_txfm.h"
|
||||
|
||||
@ -515,62 +516,9 @@ static INLINE void highbd_idct16x16_add_stage7(const int32x4_t *const step2,
|
||||
out[15] = vsubq_s32(step2[0], step2[15]);
|
||||
}
|
||||
|
||||
static INLINE void highbd_idct16x16_store_pass1(const int32x4x2_t *const out,
|
||||
int32_t *output) {
|
||||
// Save the result into output
|
||||
vst1q_s32(output + 0, out[0].val[0]);
|
||||
vst1q_s32(output + 4, out[0].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[1].val[0]);
|
||||
vst1q_s32(output + 4, out[1].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[2].val[0]);
|
||||
vst1q_s32(output + 4, out[2].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[3].val[0]);
|
||||
vst1q_s32(output + 4, out[3].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[4].val[0]);
|
||||
vst1q_s32(output + 4, out[4].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[5].val[0]);
|
||||
vst1q_s32(output + 4, out[5].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[6].val[0]);
|
||||
vst1q_s32(output + 4, out[6].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[7].val[0]);
|
||||
vst1q_s32(output + 4, out[7].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[8].val[0]);
|
||||
vst1q_s32(output + 4, out[8].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[9].val[0]);
|
||||
vst1q_s32(output + 4, out[9].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[10].val[0]);
|
||||
vst1q_s32(output + 4, out[10].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[11].val[0]);
|
||||
vst1q_s32(output + 4, out[11].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[12].val[0]);
|
||||
vst1q_s32(output + 4, out[12].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[13].val[0]);
|
||||
vst1q_s32(output + 4, out[13].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[14].val[0]);
|
||||
vst1q_s32(output + 4, out[14].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[15].val[0]);
|
||||
vst1q_s32(output + 4, out[15].val[1]);
|
||||
}
|
||||
|
||||
static void vpx_highbd_idct16x16_256_add_half1d(const int32_t *input,
|
||||
int32_t *output, uint16_t *dest,
|
||||
const int stride,
|
||||
const int bd) {
|
||||
void vpx_highbd_idct16x16_256_add_half1d(const int32_t *input, int32_t *output,
|
||||
uint16_t *dest, const int stride,
|
||||
const int bd) {
|
||||
const int32x4_t cospi_0_8_16_24 = vld1q_s32(kCospi32 + 0);
|
||||
const int32x4_t cospi_4_12_20N_28 = vld1q_s32(kCospi32 + 4);
|
||||
const int32x4_t cospi_2_30_10_22 = vld1q_s32(kCospi32 + 8);
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
|
||||
#include "./vpx_config.h"
|
||||
#include "./vpx_dsp_rtcd.h"
|
||||
#include "vpx_dsp/arm/highbd_idct_neon.h"
|
||||
#include "vpx_dsp/arm/idct_neon.h"
|
||||
#include "vpx_dsp/arm/transpose_neon.h"
|
||||
#include "vpx_dsp/txfm_common.h"
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
|
||||
#include "./vpx_config.h"
|
||||
#include "./vpx_dsp_rtcd.h"
|
||||
#include "vpx_dsp/arm/highbd_idct_neon.h"
|
||||
#include "vpx_dsp/arm/idct_neon.h"
|
||||
#include "vpx_dsp/arm/transpose_neon.h"
|
||||
#include "vpx_dsp/txfm_common.h"
|
||||
|
||||
@ -359,4 +359,116 @@ static INLINE void idct8x8_64_half1d_bd12(
|
||||
*io7 = vsubq_s32(step1[0], step2[7]);
|
||||
}
|
||||
|
||||
static INLINE void highbd_idct16x16_store_pass1(const int32x4x2_t *const out,
|
||||
int32_t *output) {
|
||||
// Save the result into output
|
||||
vst1q_s32(output + 0, out[0].val[0]);
|
||||
vst1q_s32(output + 4, out[0].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[1].val[0]);
|
||||
vst1q_s32(output + 4, out[1].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[2].val[0]);
|
||||
vst1q_s32(output + 4, out[2].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[3].val[0]);
|
||||
vst1q_s32(output + 4, out[3].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[4].val[0]);
|
||||
vst1q_s32(output + 4, out[4].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[5].val[0]);
|
||||
vst1q_s32(output + 4, out[5].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[6].val[0]);
|
||||
vst1q_s32(output + 4, out[6].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[7].val[0]);
|
||||
vst1q_s32(output + 4, out[7].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[8].val[0]);
|
||||
vst1q_s32(output + 4, out[8].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[9].val[0]);
|
||||
vst1q_s32(output + 4, out[9].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[10].val[0]);
|
||||
vst1q_s32(output + 4, out[10].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[11].val[0]);
|
||||
vst1q_s32(output + 4, out[11].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[12].val[0]);
|
||||
vst1q_s32(output + 4, out[12].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[13].val[0]);
|
||||
vst1q_s32(output + 4, out[13].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[14].val[0]);
|
||||
vst1q_s32(output + 4, out[14].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, out[15].val[0]);
|
||||
vst1q_s32(output + 4, out[15].val[1]);
|
||||
}
|
||||
|
||||
static INLINE void highbd_idct16x16_add_store(const int32x4x2_t *const out,
|
||||
uint16_t *dest, const int stride,
|
||||
const int bd) {
|
||||
// Add the result to dest
|
||||
const int16x8_t max = vdupq_n_s16((1 << bd) - 1);
|
||||
int16x8_t o[16];
|
||||
o[0] = vcombine_s16(vrshrn_n_s32(out[0].val[0], 6),
|
||||
vrshrn_n_s32(out[0].val[1], 6));
|
||||
o[1] = vcombine_s16(vrshrn_n_s32(out[1].val[0], 6),
|
||||
vrshrn_n_s32(out[1].val[1], 6));
|
||||
o[2] = vcombine_s16(vrshrn_n_s32(out[2].val[0], 6),
|
||||
vrshrn_n_s32(out[2].val[1], 6));
|
||||
o[3] = vcombine_s16(vrshrn_n_s32(out[3].val[0], 6),
|
||||
vrshrn_n_s32(out[3].val[1], 6));
|
||||
o[4] = vcombine_s16(vrshrn_n_s32(out[4].val[0], 6),
|
||||
vrshrn_n_s32(out[4].val[1], 6));
|
||||
o[5] = vcombine_s16(vrshrn_n_s32(out[5].val[0], 6),
|
||||
vrshrn_n_s32(out[5].val[1], 6));
|
||||
o[6] = vcombine_s16(vrshrn_n_s32(out[6].val[0], 6),
|
||||
vrshrn_n_s32(out[6].val[1], 6));
|
||||
o[7] = vcombine_s16(vrshrn_n_s32(out[7].val[0], 6),
|
||||
vrshrn_n_s32(out[7].val[1], 6));
|
||||
o[8] = vcombine_s16(vrshrn_n_s32(out[8].val[0], 6),
|
||||
vrshrn_n_s32(out[8].val[1], 6));
|
||||
o[9] = vcombine_s16(vrshrn_n_s32(out[9].val[0], 6),
|
||||
vrshrn_n_s32(out[9].val[1], 6));
|
||||
o[10] = vcombine_s16(vrshrn_n_s32(out[10].val[0], 6),
|
||||
vrshrn_n_s32(out[10].val[1], 6));
|
||||
o[11] = vcombine_s16(vrshrn_n_s32(out[11].val[0], 6),
|
||||
vrshrn_n_s32(out[11].val[1], 6));
|
||||
o[12] = vcombine_s16(vrshrn_n_s32(out[12].val[0], 6),
|
||||
vrshrn_n_s32(out[12].val[1], 6));
|
||||
o[13] = vcombine_s16(vrshrn_n_s32(out[13].val[0], 6),
|
||||
vrshrn_n_s32(out[13].val[1], 6));
|
||||
o[14] = vcombine_s16(vrshrn_n_s32(out[14].val[0], 6),
|
||||
vrshrn_n_s32(out[14].val[1], 6));
|
||||
o[15] = vcombine_s16(vrshrn_n_s32(out[15].val[0], 6),
|
||||
vrshrn_n_s32(out[15].val[1], 6));
|
||||
highbd_idct16x16_add8x1(o[0], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[1], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[2], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[3], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[4], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[5], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[6], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[7], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[8], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[9], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[10], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[11], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[12], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[13], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[14], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[15], max, &dest, stride);
|
||||
}
|
||||
|
||||
void vpx_highbd_idct16x16_256_add_half1d(const int32_t *input, int32_t *output,
|
||||
uint16_t *dest, const int stride,
|
||||
const int bd);
|
||||
|
||||
#endif // VPX_DSP_ARM_HIGHBD_IDCT_NEON_H_
|
||||
|
||||
@ -890,62 +890,6 @@ static INLINE void highbd_add_and_store_bd8(const int16x8_t *const a,
|
||||
highbd_idct16x16_add8x1_bd8(a[31], &out, stride);
|
||||
}
|
||||
|
||||
static INLINE void highbd_idct16x16_add_store(const int32x4x2_t *const out,
|
||||
uint16_t *dest, const int stride,
|
||||
const int bd) {
|
||||
// Add the result to dest
|
||||
const int16x8_t max = vdupq_n_s16((1 << bd) - 1);
|
||||
int16x8_t o[16];
|
||||
o[0] = vcombine_s16(vrshrn_n_s32(out[0].val[0], 6),
|
||||
vrshrn_n_s32(out[0].val[1], 6));
|
||||
o[1] = vcombine_s16(vrshrn_n_s32(out[1].val[0], 6),
|
||||
vrshrn_n_s32(out[1].val[1], 6));
|
||||
o[2] = vcombine_s16(vrshrn_n_s32(out[2].val[0], 6),
|
||||
vrshrn_n_s32(out[2].val[1], 6));
|
||||
o[3] = vcombine_s16(vrshrn_n_s32(out[3].val[0], 6),
|
||||
vrshrn_n_s32(out[3].val[1], 6));
|
||||
o[4] = vcombine_s16(vrshrn_n_s32(out[4].val[0], 6),
|
||||
vrshrn_n_s32(out[4].val[1], 6));
|
||||
o[5] = vcombine_s16(vrshrn_n_s32(out[5].val[0], 6),
|
||||
vrshrn_n_s32(out[5].val[1], 6));
|
||||
o[6] = vcombine_s16(vrshrn_n_s32(out[6].val[0], 6),
|
||||
vrshrn_n_s32(out[6].val[1], 6));
|
||||
o[7] = vcombine_s16(vrshrn_n_s32(out[7].val[0], 6),
|
||||
vrshrn_n_s32(out[7].val[1], 6));
|
||||
o[8] = vcombine_s16(vrshrn_n_s32(out[8].val[0], 6),
|
||||
vrshrn_n_s32(out[8].val[1], 6));
|
||||
o[9] = vcombine_s16(vrshrn_n_s32(out[9].val[0], 6),
|
||||
vrshrn_n_s32(out[9].val[1], 6));
|
||||
o[10] = vcombine_s16(vrshrn_n_s32(out[10].val[0], 6),
|
||||
vrshrn_n_s32(out[10].val[1], 6));
|
||||
o[11] = vcombine_s16(vrshrn_n_s32(out[11].val[0], 6),
|
||||
vrshrn_n_s32(out[11].val[1], 6));
|
||||
o[12] = vcombine_s16(vrshrn_n_s32(out[12].val[0], 6),
|
||||
vrshrn_n_s32(out[12].val[1], 6));
|
||||
o[13] = vcombine_s16(vrshrn_n_s32(out[13].val[0], 6),
|
||||
vrshrn_n_s32(out[13].val[1], 6));
|
||||
o[14] = vcombine_s16(vrshrn_n_s32(out[14].val[0], 6),
|
||||
vrshrn_n_s32(out[14].val[1], 6));
|
||||
o[15] = vcombine_s16(vrshrn_n_s32(out[15].val[0], 6),
|
||||
vrshrn_n_s32(out[15].val[1], 6));
|
||||
highbd_idct16x16_add8x1(o[0], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[1], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[2], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[3], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[4], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[5], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[6], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[7], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[8], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[9], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[10], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[11], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[12], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[13], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[14], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[15], max, &dest, stride);
|
||||
}
|
||||
|
||||
void vpx_idct16x16_256_add_half1d(const void *const input, int16_t *output,
|
||||
void *const dest, const int stride,
|
||||
const int highbd_flag);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user