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Merge changes Ica8dbe5f,I8f4e0fc6

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* changes:
  Update vp9_iht4x4_16_add_neon()
  Clean dct_const_round_shift() related neon code
This commit is contained in:
Linfeng Zhang 2018-01-29 20:16:47 +00:00 committed by Gerrit Code Review
commit 77108f5001
9 changed files with 245 additions and 391 deletions
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23
test/dct_test.cc
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@ -752,6 +752,29 @@ INSTANTIATE_TEST_CASE_P(C, TransHT, ::testing::ValuesIn(c_ht_tests));
#if !CONFIG_EMULATE_HARDWARE
#if HAVE_NEON
INSTANTIATE_TEST_CASE_P(
NEON, TransHT,
::testing::Values(
make_tuple(&vp9_fht8x8_c, &iht_wrapper<vp9_iht8x8_64_add_neon>, 8, 0,
VPX_BITS_8, 1),
make_tuple(&vp9_fht8x8_c, &iht_wrapper<vp9_iht8x8_64_add_neon>, 8, 1,
VPX_BITS_8, 1),
make_tuple(&vp9_fht8x8_c, &iht_wrapper<vp9_iht8x8_64_add_neon>, 8, 2,
VPX_BITS_8, 1),
make_tuple(&vp9_fht8x8_c, &iht_wrapper<vp9_iht8x8_64_add_neon>, 8, 3,
VPX_BITS_8, 1),
make_tuple(&vp9_fht4x4_c, &iht_wrapper<vp9_iht4x4_16_add_neon>, 4, 0,
VPX_BITS_8, 1),
make_tuple(&vp9_fht4x4_c, &iht_wrapper<vp9_iht4x4_16_add_neon>, 4, 1,
VPX_BITS_8, 1),
make_tuple(&vp9_fht4x4_c, &iht_wrapper<vp9_iht4x4_16_add_neon>, 4, 2,
VPX_BITS_8, 1),
make_tuple(&vp9_fht4x4_c, &iht_wrapper<vp9_iht4x4_16_add_neon>, 4, 3,
VPX_BITS_8, 1)));
#endif // HAVE_NEON
#if HAVE_SSE2
INSTANTIATE_TEST_CASE_P(
SSE2, TransHT,

255
vp9/common/arm/neon/vp9_iht4x4_add_neon.c
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@ -14,206 +14,103 @@
#include "./vp9_rtcd.h"
#include "./vpx_config.h"
#include "vp9/common/vp9_common.h"
#include "vpx_dsp/arm/idct_neon.h"
#include "vpx_dsp/arm/mem_neon.h"
#include "vpx_dsp/txfm_common.h"
static INLINE void TRANSPOSE4X4(int16x8_t *q8s16, int16x8_t *q9s16) {
int32x4_t q8s32, q9s32;
int16x4x2_t d0x2s16, d1x2s16;
int32x4x2_t q0x2s32;
static INLINE void iadst4(int16x8_t *const io) {
const int32x4_t c3 = vdupq_n_s32(sinpi_3_9);
int16x4_t c[5], x[4];
int32x4_t s[8], output[4];
d0x2s16 = vtrn_s16(vget_low_s16(*q8s16), vget_high_s16(*q8s16));
d1x2s16 = vtrn_s16(vget_low_s16(*q9s16), vget_high_s16(*q9s16));
c[1] = vdup_n_s16(sinpi_1_9);
c[2] = vdup_n_s16(sinpi_2_9);
c[3] = vdup_n_s16(sinpi_3_9);
c[4] = vdup_n_s16(sinpi_4_9);
q8s32 = vreinterpretq_s32_s16(vcombine_s16(d0x2s16.val[0], d0x2s16.val[1]));
q9s32 = vreinterpretq_s32_s16(vcombine_s16(d1x2s16.val[0], d1x2s16.val[1]));
q0x2s32 = vtrnq_s32(q8s32, q9s32);
x[0] = vget_low_s16(io[0]);
x[1] = vget_low_s16(io[1]);
x[2] = vget_high_s16(io[0]);
x[3] = vget_high_s16(io[1]);
*q8s16 = vreinterpretq_s16_s32(q0x2s32.val[0]);
*q9s16 = vreinterpretq_s16_s32(q0x2s32.val[1]);
}
s[0] = vmull_s16(c[1], x[0]);
s[1] = vmull_s16(c[2], x[0]);
s[2] = vmull_s16(c[3], x[1]);
s[3] = vmull_s16(c[4], x[2]);
s[4] = vmull_s16(c[1], x[2]);
s[5] = vmull_s16(c[2], x[3]);
s[6] = vmull_s16(c[4], x[3]);
s[7] = vaddl_s16(x[0], x[3]);
s[7] = vsubw_s16(s[7], x[2]);
static INLINE void GENERATE_COSINE_CONSTANTS(int16x4_t *d0s16, int16x4_t *d1s16,
int16x4_t *d2s16) {
*d0s16 = vdup_n_s16(cospi_8_64);
*d1s16 = vdup_n_s16(cospi_16_64);
*d2s16 = vdup_n_s16(cospi_24_64);
}
s[0] = vaddq_s32(s[0], s[3]);
s[0] = vaddq_s32(s[0], s[5]);
s[1] = vsubq_s32(s[1], s[4]);
s[1] = vsubq_s32(s[1], s[6]);
s[3] = s[2];
s[2] = vmulq_s32(c3, s[7]);
static INLINE void GENERATE_SINE_CONSTANTS(int16x4_t *d3s16, int16x4_t *d4s16,
int16x4_t *d5s16, int16x8_t *q3s16) {
*d3s16 = vdup_n_s16(sinpi_1_9);
*d4s16 = vdup_n_s16(sinpi_2_9);
*q3s16 = vdupq_n_s16(sinpi_3_9);
*d5s16 = vdup_n_s16(sinpi_4_9);
}
static INLINE void IDCT4x4_1D(int16x4_t *d0s16, int16x4_t *d1s16,
int16x4_t *d2s16, int16x8_t *q8s16,
int16x8_t *q9s16) {
int16x4_t d16s16, d17s16, d18s16, d19s16, d23s16, d24s16;
int16x4_t d26s16, d27s16, d28s16, d29s16;
int32x4_t q10s32, q13s32, q14s32, q15s32;
int16x8_t q13s16, q14s16;
d16s16 = vget_low_s16(*q8s16);
d17s16 = vget_high_s16(*q8s16);
d18s16 = vget_low_s16(*q9s16);
d19s16 = vget_high_s16(*q9s16);
d23s16 = vadd_s16(d16s16, d18s16);
d24s16 = vsub_s16(d16s16, d18s16);
q15s32 = vmull_s16(d17s16, *d2s16);
q10s32 = vmull_s16(d17s16, *d0s16);
q13s32 = vmull_s16(d23s16, *d1s16);
q14s32 = vmull_s16(d24s16, *d1s16);
q15s32 = vmlsl_s16(q15s32, d19s16, *d0s16);
q10s32 = vmlal_s16(q10s32, d19s16, *d2s16);
d26s16 = vrshrn_n_s32(q13s32, 14);
d27s16 = vrshrn_n_s32(q14s32, 14);
d29s16 = vrshrn_n_s32(q15s32, 14);
d28s16 = vrshrn_n_s32(q10s32, 14);
q13s16 = vcombine_s16(d26s16, d27s16);
q14s16 = vcombine_s16(d28s16, d29s16);
*q8s16 = vaddq_s16(q13s16, q14s16);
*q9s16 = vsubq_s16(q13s16, q14s16);
*q9s16 = vcombine_s16(vget_high_s16(*q9s16), vget_low_s16(*q9s16)); // vswp
}
static INLINE void IADST4x4_1D(int16x4_t *d3s16, int16x4_t *d4s16,
int16x4_t *d5s16, int16x8_t *q3s16,
int16x8_t *q8s16, int16x8_t *q9s16) {
int16x4_t d6s16, d16s16, d17s16, d18s16, d19s16;
int32x4_t q8s32, q9s32, q10s32, q11s32, q12s32, q13s32, q14s32, q15s32;
d6s16 = vget_low_s16(*q3s16);
d16s16 = vget_low_s16(*q8s16);
d17s16 = vget_high_s16(*q8s16);
d18s16 = vget_low_s16(*q9s16);
d19s16 = vget_high_s16(*q9s16);
q10s32 = vmull_s16(*d3s16, d16s16);
q11s32 = vmull_s16(*d4s16, d16s16);
q12s32 = vmull_s16(d6s16, d17s16);
q13s32 = vmull_s16(*d5s16, d18s16);
q14s32 = vmull_s16(*d3s16, d18s16);
q15s32 = vmovl_s16(d16s16);
q15s32 = vaddw_s16(q15s32, d19s16);
q8s32 = vmull_s16(*d4s16, d19s16);
q15s32 = vsubw_s16(q15s32, d18s16);
q9s32 = vmull_s16(*d5s16, d19s16);
q10s32 = vaddq_s32(q10s32, q13s32);
q10s32 = vaddq_s32(q10s32, q8s32);
q11s32 = vsubq_s32(q11s32, q14s32);
q8s32 = vdupq_n_s32(sinpi_3_9);
q11s32 = vsubq_s32(q11s32, q9s32);
q15s32 = vmulq_s32(q15s32, q8s32);
q13s32 = vaddq_s32(q10s32, q12s32);
q10s32 = vaddq_s32(q10s32, q11s32);
q14s32 = vaddq_s32(q11s32, q12s32);
q10s32 = vsubq_s32(q10s32, q12s32);
d16s16 = vrshrn_n_s32(q13s32, 14);
d17s16 = vrshrn_n_s32(q14s32, 14);
d18s16 = vrshrn_n_s32(q15s32, 14);
d19s16 = vrshrn_n_s32(q10s32, 14);
*q8s16 = vcombine_s16(d16s16, d17s16);
*q9s16 = vcombine_s16(d18s16, d19s16);
output[0] = vaddq_s32(s[0], s[3]);
output[1] = vaddq_s32(s[1], s[3]);
output[2] = s[2];
output[3] = vaddq_s32(s[0], s[1]);
output[3] = vsubq_s32(output[3], s[3]);
dct_const_round_shift_low_8_dual(output, &io[0], &io[1]);
}
void vp9_iht4x4_16_add_neon(const tran_low_t *input, uint8_t *dest, int stride,
int tx_type) {
uint8x8_t d26u8, d27u8;
int16x4_t d0s16, d1s16, d2s16, d3s16, d4s16, d5s16;
uint32x2_t d26u32, d27u32;
int16x8_t q3s16, q8s16, q9s16;
uint16x8_t q8u16, q9u16;
int16x8_t a[2];
uint8x8_t s[2], d[2];
uint16x8_t sum[2];
d26u32 = d27u32 = vdup_n_u32(0);
assert(!((intptr_t)dest % sizeof(uint32_t)));
assert(!(stride % sizeof(uint32_t)));
q8s16 = vld1q_s16(input);
q9s16 = vld1q_s16(input + 8);
TRANSPOSE4X4(&q8s16, &q9s16);
a[0] = load_tran_low_to_s16q(input);
a[1] = load_tran_low_to_s16q(input + 8);
transpose_s16_4x4q(&a[0], &a[1]);
switch (tx_type) {
case 0: // idct_idct is not supported. Fall back to C
vp9_iht4x4_16_add_c(input, dest, stride, tx_type);
return;
case 1: // iadst_idct
// generate constants
GENERATE_COSINE_CONSTANTS(&d0s16, &d1s16, &d2s16);
GENERATE_SINE_CONSTANTS(&d3s16, &d4s16, &d5s16, &q3s16);
// first transform rows
IDCT4x4_1D(&d0s16, &d1s16, &d2s16, &q8s16, &q9s16);
// transpose the matrix
TRANSPOSE4X4(&q8s16, &q9s16);
// then transform columns
IADST4x4_1D(&d3s16, &d4s16, &d5s16, &q3s16, &q8s16, &q9s16);
case 0: // DCT_DCT
idct4x4_16_kernel_bd8(a);
a[1] = vcombine_s16(vget_high_s16(a[1]), vget_low_s16(a[1]));
transpose_s16_4x4q(&a[0], &a[1]);
idct4x4_16_kernel_bd8(a);
a[1] = vcombine_s16(vget_high_s16(a[1]), vget_low_s16(a[1]));
break;
case 2: // idct_iadst
// generate constantsyy
GENERATE_COSINE_CONSTANTS(&d0s16, &d1s16, &d2s16);
GENERATE_SINE_CONSTANTS(&d3s16, &d4s16, &d5s16, &q3s16);
// first transform rows
IADST4x4_1D(&d3s16, &d4s16, &d5s16, &q3s16, &q8s16, &q9s16);
// transpose the matrix
TRANSPOSE4X4(&q8s16, &q9s16);
// then transform columns
IDCT4x4_1D(&d0s16, &d1s16, &d2s16, &q8s16, &q9s16);
case 1: // ADST_DCT
idct4x4_16_kernel_bd8(a);
a[1] = vcombine_s16(vget_high_s16(a[1]), vget_low_s16(a[1]));
transpose_s16_4x4q(&a[0], &a[1]);
iadst4(a);
break;
case 3: // iadst_iadst
// generate constants
GENERATE_SINE_CONSTANTS(&d3s16, &d4s16, &d5s16, &q3s16);
// first transform rows
IADST4x4_1D(&d3s16, &d4s16, &d5s16, &q3s16, &q8s16, &q9s16);
// transpose the matrix
TRANSPOSE4X4(&q8s16, &q9s16);
// then transform columns
IADST4x4_1D(&d3s16, &d4s16, &d5s16, &q3s16, &q8s16, &q9s16);
case 2: // DCT_ADST
iadst4(a);
transpose_s16_4x4q(&a[0], &a[1]);
idct4x4_16_kernel_bd8(a);
a[1] = vcombine_s16(vget_high_s16(a[1]), vget_low_s16(a[1]));
break;
default: // iadst_idct
assert(0);
case 3: // ADST_ADST
iadst4(a);
transpose_s16_4x4q(&a[0], &a[1]);
iadst4(a);
break;
default: assert(0); break;
}
q8s16 = vrshrq_n_s16(q8s16, 4);
q9s16 = vrshrq_n_s16(q9s16, 4);
d26u32 = vld1_lane_u32((const uint32_t *)dest, d26u32, 0);
dest += stride;
d26u32 = vld1_lane_u32((const uint32_t *)dest, d26u32, 1);
dest += stride;
d27u32 = vld1_lane_u32((const uint32_t *)dest, d27u32, 0);
dest += stride;
d27u32 = vld1_lane_u32((const uint32_t *)dest, d27u32, 1);
q8u16 = vaddw_u8(vreinterpretq_u16_s16(q8s16), vreinterpret_u8_u32(d26u32));
q9u16 = vaddw_u8(vreinterpretq_u16_s16(q9s16), vreinterpret_u8_u32(d27u32));
d26u8 = vqmovun_s16(vreinterpretq_s16_u16(q8u16));
d27u8 = vqmovun_s16(vreinterpretq_s16_u16(q9u16));
vst1_lane_u32((uint32_t *)dest, vreinterpret_u32_u8(d27u8), 1);
dest -= stride;
vst1_lane_u32((uint32_t *)dest, vreinterpret_u32_u8(d27u8), 0);
dest -= stride;
vst1_lane_u32((uint32_t *)dest, vreinterpret_u32_u8(d26u8), 1);
dest -= stride;
vst1_lane_u32((uint32_t *)dest, vreinterpret_u32_u8(d26u8), 0);
a[0] = vrshrq_n_s16(a[0], 4);
a[1] = vrshrq_n_s16(a[1], 4);
s[0] = load_u8(dest, stride);
s[1] = load_u8(dest + 2 * stride, stride);
sum[0] = vaddw_u8(vreinterpretq_u16_s16(a[0]), s[0]);
sum[1] = vaddw_u8(vreinterpretq_u16_s16(a[1]), s[1]);
d[0] = vqmovun_s16(vreinterpretq_s16_u16(sum[0]));
d[1] = vqmovun_s16(vreinterpretq_s16_u16(sum[1]));
store_u8(dest, stride, d[0]);
store_u8(dest + 2 * stride, stride, d[1]);
}

17
vp9/common/arm/neon/vp9_iht8x8_add_neon.c
View File

@ -14,6 +14,7 @@
#include "./vp9_rtcd.h"
#include "./vpx_config.h"
#include "vp9/common/vp9_common.h"
#include "vpx_dsp/arm/mem_neon.h"
#include "vpx_dsp/arm/transpose_neon.h"
static int16_t cospi_2_64 = 16305;
@ -415,14 +416,14 @@ void vp9_iht8x8_64_add_neon(const tran_low_t *input, uint8_t *dest, int stride,
int16x8_t q8s16, q9s16, q10s16, q11s16, q12s16, q13s16, q14s16, q15s16;
uint16x8_t q8u16, q9u16, q10u16, q11u16;
q8s16 = vld1q_s16(input);
q9s16 = vld1q_s16(input + 8);
q10s16 = vld1q_s16(input + 8 * 2);
q11s16 = vld1q_s16(input + 8 * 3);
q12s16 = vld1q_s16(input + 8 * 4);
q13s16 = vld1q_s16(input + 8 * 5);
q14s16 = vld1q_s16(input + 8 * 6);
q15s16 = vld1q_s16(input + 8 * 7);
q8s16 = load_tran_low_to_s16q(input);
q9s16 = load_tran_low_to_s16q(input + 8);
q10s16 = load_tran_low_to_s16q(input + 8 * 2);
q11s16 = load_tran_low_to_s16q(input + 8 * 3);
q12s16 = load_tran_low_to_s16q(input + 8 * 4);
q13s16 = load_tran_low_to_s16q(input + 8 * 5);
q14s16 = load_tran_low_to_s16q(input + 8 * 6);
q15s16 = load_tran_low_to_s16q(input + 8 * 7);
transpose_s16_8x8(&q8s16, &q9s16, &q10s16, &q11s16, &q12s16, &q13s16, &q14s16,
&q15s16);

8
vp9/common/vp9_rtcd_defs.pl
View File

@ -67,13 +67,13 @@ add_proto qw/void vp9_iht16x16_256_add/, "const tran_low_t *input, uint8_t *outp
if (vpx_config("CONFIG_EMULATE_HARDWARE") ne "yes") {
# Note that there are more specializations appended when
# CONFIG_VP9_HIGHBITDEPTH is off.
specialize qw/vp9_iht4x4_16_add sse2/;
specialize qw/vp9_iht8x8_64_add sse2/;
specialize qw/vp9_iht4x4_16_add neon sse2/;
specialize qw/vp9_iht8x8_64_add neon sse2/;
specialize qw/vp9_iht16x16_256_add sse2/;
if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") ne "yes") {
# Note that these specializations are appended to the above ones.
specialize qw/vp9_iht4x4_16_add neon dspr2 msa/;
specialize qw/vp9_iht8x8_64_add neon dspr2 msa/;
specialize qw/vp9_iht4x4_16_add dspr2 msa/;
specialize qw/vp9_iht8x8_64_add dspr2 msa/;
specialize qw/vp9_iht16x16_256_add dspr2 msa/;
}
}

12
vp9/vp9_common.mk
View File

@ -64,10 +64,12 @@ VP9_COMMON_SRCS-$(CONFIG_VP9_POSTPROC) += common/vp9_postproc.c
VP9_COMMON_SRCS-$(CONFIG_VP9_POSTPROC) += common/vp9_mfqe.h
VP9_COMMON_SRCS-$(CONFIG_VP9_POSTPROC) += common/vp9_mfqe.c
VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_idct4x4_msa.c
VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_idct8x8_msa.c
VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_idct16x16_msa.c
VP9_COMMON_SRCS-$(HAVE_SSE2) += common/x86/vp9_idct_intrin_sse2.c
VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_idct4x4_msa.c
VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_idct8x8_msa.c
VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_idct16x16_msa.c
VP9_COMMON_SRCS-$(HAVE_SSE2) += common/x86/vp9_idct_intrin_sse2.c
VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_iht4x4_add_neon.c
VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_iht8x8_add_neon.c
ifeq ($(CONFIG_VP9_POSTPROC),yes)
VP9_COMMON_SRCS-$(HAVE_MSA) += common/mips/msa/vp9_mfqe_msa.c
@ -78,8 +80,6 @@ ifneq ($(CONFIG_VP9_HIGHBITDEPTH),yes)
VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_itrans4_dspr2.c
VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_itrans8_dspr2.c
VP9_COMMON_SRCS-$(HAVE_DSPR2) += common/mips/dspr2/vp9_itrans16_dspr2.c
VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_iht4x4_add_neon.c
VP9_COMMON_SRCS-$(HAVE_NEON) += common/arm/neon/vp9_iht8x8_add_neon.c
else
VP9_COMMON_SRCS-$(HAVE_SSE4_1) += common/x86/vp9_highbd_iht4x4_add_sse4.c
VP9_COMMON_SRCS-$(HAVE_SSE4_1) += common/x86/vp9_highbd_iht8x8_add_sse4.c

95
vpx_dsp/arm/highbd_idct16x16_add_neon.c
View File

@ -14,58 +14,33 @@
#include "vpx_dsp/arm/idct_neon.h"
#include "vpx_dsp/inv_txfm.h"
static INLINE void highbd_idct16x16_add_wrap_low_8x2(const int64x2x2_t *const t,
int32x4x2_t *const d0,
int32x4x2_t *const d1) {
int32x2x2_t t32[4];
static INLINE int32x4_t dct_const_round_shift_high_4(const int64x2x2_t in) {
int32x2x2_t t32;
t32[0].val[0] = vrshrn_n_s64(t[0].val[0], DCT_CONST_BITS);
t32[0].val[1] = vrshrn_n_s64(t[0].val[1], DCT_CONST_BITS);
t32[1].val[0] = vrshrn_n_s64(t[1].val[0], DCT_CONST_BITS);
t32[1].val[1] = vrshrn_n_s64(t[1].val[1], DCT_CONST_BITS);
t32[2].val[0] = vrshrn_n_s64(t[2].val[0], DCT_CONST_BITS);
t32[2].val[1] = vrshrn_n_s64(t[2].val[1], DCT_CONST_BITS);
t32[3].val[0] = vrshrn_n_s64(t[3].val[0], DCT_CONST_BITS);
t32[3].val[1] = vrshrn_n_s64(t[3].val[1], DCT_CONST_BITS);
d0->val[0] = vcombine_s32(t32[0].val[0], t32[0].val[1]);
d0->val[1] = vcombine_s32(t32[1].val[0], t32[1].val[1]);
d1->val[0] = vcombine_s32(t32[2].val[0], t32[2].val[1]);
d1->val[1] = vcombine_s32(t32[3].val[0], t32[3].val[1]);
t32.val[0] = vrshrn_n_s64(in.val[0], DCT_CONST_BITS);
t32.val[1] = vrshrn_n_s64(in.val[1], DCT_CONST_BITS);
return vcombine_s32(t32.val[0], t32.val[1]);
}
static INLINE void highbd_idct16x16_add_wrap_low_4x2(const int64x2x2_t *const t,
int32x4_t *const d0,
int32x4_t *const d1) {
int32x2x2_t t32[2];
t32[0].val[0] = vrshrn_n_s64(t[0].val[0], DCT_CONST_BITS);
t32[0].val[1] = vrshrn_n_s64(t[0].val[1], DCT_CONST_BITS);
t32[1].val[0] = vrshrn_n_s64(t[1].val[0], DCT_CONST_BITS);
t32[1].val[1] = vrshrn_n_s64(t[1].val[1], DCT_CONST_BITS);
*d0 = vcombine_s32(t32[0].val[0], t32[0].val[1]);
*d1 = vcombine_s32(t32[1].val[0], t32[1].val[1]);
static INLINE void dct_const_round_shift_high_4_dual(
const int64x2x2_t *const in, int32x4_t *const d0, int32x4_t *const d1) {
*d0 = dct_const_round_shift_high_4(in[0]);
*d1 = dct_const_round_shift_high_4(in[1]);
}
static INLINE int32x4x2_t
highbd_idct16x16_add_wrap_low_8x1(const int64x2x2_t *const t) {
int32x2x2_t t32[2];
int32x4x2_t d;
t32[0].val[0] = vrshrn_n_s64(t[0].val[0], DCT_CONST_BITS);
t32[0].val[1] = vrshrn_n_s64(t[0].val[1], DCT_CONST_BITS);
t32[1].val[0] = vrshrn_n_s64(t[1].val[0], DCT_CONST_BITS);
t32[1].val[1] = vrshrn_n_s64(t[1].val[1], DCT_CONST_BITS);
d.val[0] = vcombine_s32(t32[0].val[0], t32[0].val[1]);
d.val[1] = vcombine_s32(t32[1].val[0], t32[1].val[1]);
return d;
dct_const_round_shift_high_4x2_int64x2x2(const int64x2x2_t *const in) {
int32x4x2_t out;
out.val[0] = dct_const_round_shift_high_4(in[0]);
out.val[1] = dct_const_round_shift_high_4(in[1]);
return out;
}
static INLINE int32x4_t highbd_idct16x16_add_wrap_low_4x1(const int64x2x2_t t) {
int32x2x2_t t32;
t32.val[0] = vrshrn_n_s64(t.val[0], DCT_CONST_BITS);
t32.val[1] = vrshrn_n_s64(t.val[1], DCT_CONST_BITS);
return vcombine_s32(t32.val[0], t32.val[1]);
static INLINE void dct_const_round_shift_high_4x2x2(const int64x2x2_t *const in,
int32x4x2_t *const d0,
int32x4x2_t *const d1) {
*d0 = dct_const_round_shift_high_4x2_int64x2x2(in + 0);
*d1 = dct_const_round_shift_high_4x2_int64x2x2(in + 2);
}
static INLINE void highbd_idct_cospi_2_30(const int32x4x2_t s0,
@ -107,7 +82,7 @@ static INLINE void highbd_idct_cospi_2_30(const int32x4x2_t s0,
vget_low_s32(cospi_2_30_10_22), 0);
t[3].val[1] = vmlal_lane_s32(t[3].val[1], vget_high_s32(s0.val[1]),
vget_low_s32(cospi_2_30_10_22), 0);
highbd_idct16x16_add_wrap_low_8x2(t, d0, d1);
dct_const_round_shift_high_4x2x2(t, d0, d1);
}
static INLINE void highbd_idct_cospi_4_28(const int32x4x2_t s0,
@ -149,7 +124,7 @@ static INLINE void highbd_idct_cospi_4_28(const int32x4x2_t s0,
vget_low_s32(cospi_4_12_20N_28), 0);
t[3].val[1] = vmlal_lane_s32(t[3].val[1], vget_high_s32(s0.val[1]),
vget_low_s32(cospi_4_12_20N_28), 0);
highbd_idct16x16_add_wrap_low_8x2(t, d0, d1);
dct_const_round_shift_high_4x2x2(t, d0, d1);
}
static INLINE void highbd_idct_cospi_6_26(const int32x4x2_t s0,
@ -191,7 +166,7 @@ static INLINE void highbd_idct_cospi_6_26(const int32x4x2_t s0,
vget_low_s32(cospi_6_26N_14_18N), 1);
t[3].val[1] = vmlsl_lane_s32(t[3].val[1], vget_high_s32(s0.val[1]),
vget_low_s32(cospi_6_26N_14_18N), 1);
highbd_idct16x16_add_wrap_low_8x2(t, d0, d1);
dct_const_round_shift_high_4x2x2(t, d0, d1);
}
static INLINE void highbd_idct_cospi_10_22(const int32x4x2_t s0,
@ -233,7 +208,7 @@ static INLINE void highbd_idct_cospi_10_22(const int32x4x2_t s0,
vget_high_s32(cospi_2_30_10_22), 0);
t[3].val[1] = vmlal_lane_s32(t[3].val[1], vget_high_s32(s0.val[1]),
vget_high_s32(cospi_2_30_10_22), 0);
highbd_idct16x16_add_wrap_low_8x2(t, d0, d1);
dct_const_round_shift_high_4x2x2(t, d0, d1);
}
static INLINE void highbd_idct_cospi_12_20(const int32x4x2_t s0,
@ -275,7 +250,7 @@ static INLINE void highbd_idct_cospi_12_20(const int32x4x2_t s0,
vget_high_s32(cospi_4_12_20N_28), 0);
t[3].val[1] = vmlsl_lane_s32(t[3].val[1], vget_high_s32(s0.val[1]),
vget_high_s32(cospi_4_12_20N_28), 0);
highbd_idct16x16_add_wrap_low_8x2(t, d0, d1);
dct_const_round_shift_high_4x2x2(t, d0, d1);
}
static INLINE void highbd_idct_cospi_14_18(const int32x4x2_t s0,
@ -317,7 +292,7 @@ static INLINE void highbd_idct_cospi_14_18(const int32x4x2_t s0,
vget_high_s32(cospi_6_26N_14_18N), 1);
t[3].val[1] = vmlsl_lane_s32(t[3].val[1], vget_high_s32(s0.val[1]),
vget_high_s32(cospi_6_26N_14_18N), 1);
highbd_idct16x16_add_wrap_low_8x2(t, d0, d1);
dct_const_round_shift_high_4x2x2(t, d0, d1);
}
static INLINE void highbd_idct_cospi_8_24_q_kernel(
@ -386,7 +361,7 @@ static INLINE void highbd_idct_cospi_8_24_q(const int32x4x2_t s0,
int64x2x2_t t[4];
highbd_idct_cospi_8_24_q_kernel(s0, s1, cospi_0_8_16_24, t);
highbd_idct16x16_add_wrap_low_8x2(t, d0, d1);
dct_const_round_shift_high_4x2x2(t, d0, d1);
}
static INLINE void highbd_idct_cospi_8_24_d(const int32x4_t s0,
@ -397,7 +372,7 @@ static INLINE void highbd_idct_cospi_8_24_d(const int32x4_t s0,
int64x2x2_t t[2];
highbd_idct_cospi_8_24_d_kernel(s0, s1, cospi_0_8_16_24, t);
highbd_idct16x16_add_wrap_low_4x2(t, d0, d1);
dct_const_round_shift_high_4_dual(t, d0, d1);
}
static INLINE void highbd_idct_cospi_8_24_neg_q(const int32x4x2_t s0,
@ -412,7 +387,7 @@ static INLINE void highbd_idct_cospi_8_24_neg_q(const int32x4x2_t s0,
t[2].val[1] = vsubq_s64(vdupq_n_s64(0), t[2].val[1]);
t[3].val[0] = vsubq_s64(vdupq_n_s64(0), t[3].val[0]);
t[3].val[1] = vsubq_s64(vdupq_n_s64(0), t[3].val[1]);
highbd_idct16x16_add_wrap_low_8x2(t, d0, d1);
dct_const_round_shift_high_4x2x2(t, d0, d1);
}
static INLINE void highbd_idct_cospi_8_24_neg_d(const int32x4_t s0,
@ -425,7 +400,7 @@ static INLINE void highbd_idct_cospi_8_24_neg_d(const int32x4_t s0,
highbd_idct_cospi_8_24_d_kernel(s0, s1, cospi_0_8_16_24, t);
t[1].val[0] = vsubq_s64(vdupq_n_s64(0), t[1].val[0]);
t[1].val[1] = vsubq_s64(vdupq_n_s64(0), t[1].val[1]);
highbd_idct16x16_add_wrap_low_4x2(t, d0, d1);
dct_const_round_shift_high_4_dual(t, d0, d1);
}
static INLINE void highbd_idct_cospi_16_16_q(const int32x4x2_t s0,
@ -459,7 +434,7 @@ static INLINE void highbd_idct_cospi_16_16_q(const int32x4x2_t s0,
vget_high_s32(cospi_0_8_16_24), 0);
t[3].val[1] = vmlal_lane_s32(t[5].val[1], vget_high_s32(s0.val[1]),
vget_high_s32(cospi_0_8_16_24), 0);
highbd_idct16x16_add_wrap_low_8x2(t, d0, d1);
dct_const_round_shift_high_4x2x2(t, d0, d1);
}
static INLINE void highbd_idct_cospi_16_16_d(const int32x4_t s0,
@ -481,7 +456,7 @@ static INLINE void highbd_idct_cospi_16_16_d(const int32x4_t s0,
vget_high_s32(cospi_0_8_16_24), 0);
t[1].val[1] = vmlal_lane_s32(t[2].val[1], vget_high_s32(s0),
vget_high_s32(cospi_0_8_16_24), 0);
highbd_idct16x16_add_wrap_low_4x2(t, d0, d1);
dct_const_round_shift_high_4_dual(t, d0, d1);
}
static INLINE void highbd_idct16x16_add_stage7_dual(
@ -815,7 +790,7 @@ static INLINE int32x4x2_t highbd_idct_cospi_lane0_dual(const int32x4x2_t s,
t[0].val[1] = vmull_lane_s32(vget_high_s32(s.val[0]), coef, 0);
t[1].val[0] = vmull_lane_s32(vget_low_s32(s.val[1]), coef, 0);
t[1].val[1] = vmull_lane_s32(vget_high_s32(s.val[1]), coef, 0);
return highbd_idct16x16_add_wrap_low_8x1(t);
return dct_const_round_shift_high_4x2_int64x2x2(t);
}
static INLINE int32x4_t highbd_idct_cospi_lane0(const int32x4_t s,
@ -824,7 +799,7 @@ static INLINE int32x4_t highbd_idct_cospi_lane0(const int32x4_t s,
t.val[0] = vmull_lane_s32(vget_low_s32(s), coef, 0);
t.val[1] = vmull_lane_s32(vget_high_s32(s), coef, 0);
return highbd_idct16x16_add_wrap_low_4x1(t);
return dct_const_round_shift_high_4(t);
}
static INLINE int32x4x2_t highbd_idct_cospi_lane1_dual(const int32x4x2_t s,
@ -835,7 +810,7 @@ static INLINE int32x4x2_t highbd_idct_cospi_lane1_dual(const int32x4x2_t s,
t[0].val[1] = vmull_lane_s32(vget_high_s32(s.val[0]), coef, 1);
t[1].val[0] = vmull_lane_s32(vget_low_s32(s.val[1]), coef, 1);
t[1].val[1] = vmull_lane_s32(vget_high_s32(s.val[1]), coef, 1);
return highbd_idct16x16_add_wrap_low_8x1(t);
return dct_const_round_shift_high_4x2_int64x2x2(t);
}
static INLINE int32x4_t highbd_idct_cospi_lane1(const int32x4_t s,
@ -844,7 +819,7 @@ static INLINE int32x4_t highbd_idct_cospi_lane1(const int32x4_t s,
t.val[0] = vmull_lane_s32(vget_low_s32(s), coef, 1);
t.val[1] = vmull_lane_s32(vget_high_s32(s), coef, 1);
return highbd_idct16x16_add_wrap_low_4x1(t);
return dct_const_round_shift_high_4(t);
}
static void vpx_highbd_idct16x16_38_add_half1d(const int32_t *input,

6
vpx_dsp/arm/highbd_idct4x4_add_neon.c
View File

@ -138,16 +138,14 @@ void vpx_highbd_idct4x4_16_add_neon(const tran_low_t *input, uint16_t *dest,
c[3] = vld1q_s32(input + 12);
if (bd == 8) {
const int16x4_t cospis = vld1_s16(kCospi);
// Rows
a[0] = vcombine_s16(vmovn_s32(c[0]), vmovn_s32(c[1]));
a[1] = vcombine_s16(vmovn_s32(c[2]), vmovn_s32(c[3]));
idct4x4_16_kernel_bd8(cospis, a);
transpose_idct4x4_16_bd8(a);
// Columns
a[1] = vcombine_s16(vget_high_s16(a[1]), vget_low_s16(a[1]));
idct4x4_16_kernel_bd8(cospis, a);
transpose_idct4x4_16_bd8(a);
a[0] = vrshrq_n_s16(a[0], 4);
a[1] = vrshrq_n_s16(a[1], 4);
} else {

5
vpx_dsp/arm/idct4x4_add_neon.c
View File

@ -19,7 +19,6 @@
void vpx_idct4x4_16_add_neon(const tran_low_t *input, uint8_t *dest,
int stride) {
const uint8_t *dst = dest;
const int16x4_t cospis = vld1_s16(kCospi);
uint32x2_t s32 = vdup_n_u32(0);
int16x8_t a[2];
uint8x8_t s, d[2];
@ -31,11 +30,11 @@ void vpx_idct4x4_16_add_neon(const tran_low_t *input, uint8_t *dest,
// Rows
a[0] = load_tran_low_to_s16q(input);
a[1] = load_tran_low_to_s16q(input + 8);
idct4x4_16_kernel_bd8(cospis, a);
transpose_idct4x4_16_bd8(a);
// Columns
a[1] = vcombine_s16(vget_high_s16(a[1]), vget_low_s16(a[1]));
idct4x4_16_kernel_bd8(cospis, a);
transpose_idct4x4_16_bd8(a);
a[0] = vrshrq_n_s16(a[0], 4);
a[1] = vrshrq_n_s16(a[1], 4);

215
vpx_dsp/arm/idct_neon.h
View File

@ -78,6 +78,28 @@ static INLINE int32x4x2_t highbd_idct_sub_dual(const int32x4x2_t s0,
//------------------------------------------------------------------------------
static INLINE int16x8_t dct_const_round_shift_low_8(const int32x4_t *const in) {
return vcombine_s16(vrshrn_n_s32(in[0], DCT_CONST_BITS),
vrshrn_n_s32(in[1], DCT_CONST_BITS));
}
static INLINE void dct_const_round_shift_low_8_dual(const int32x4_t *const t32,
int16x8_t *const d0,
int16x8_t *const d1) {
*d0 = dct_const_round_shift_low_8(t32 + 0);
*d1 = dct_const_round_shift_low_8(t32 + 2);
}
static INLINE int32x4x2_t
dct_const_round_shift_high_4x2(const int64x2_t *const in) {
int32x4x2_t out;
out.val[0] = vcombine_s32(vrshrn_n_s64(in[0], DCT_CONST_BITS),
vrshrn_n_s64(in[1], DCT_CONST_BITS));
out.val[1] = vcombine_s32(vrshrn_n_s64(in[2], DCT_CONST_BITS),
vrshrn_n_s64(in[3], DCT_CONST_BITS));
return out;
}
// Multiply a by a_const. Saturate, shift and narrow by DCT_CONST_BITS.
static INLINE int16x8_t multiply_shift_and_narrow_s16(const int16x8_t a,
const int16_t a_const) {
@ -102,24 +124,24 @@ static INLINE int16x8_t add_multiply_shift_and_narrow_s16(
// input) this function can not use vaddq_s16.
// In order to match existing behavior and intentionally out of range tests,
// expand the addition up to 32 bits to prevent truncation.
int32x4_t temp_low = vaddl_s16(vget_low_s16(a), vget_low_s16(b));
int32x4_t temp_high = vaddl_s16(vget_high_s16(a), vget_high_s16(b));
temp_low = vmulq_n_s32(temp_low, ab_const);
temp_high = vmulq_n_s32(temp_high, ab_const);
return vcombine_s16(vrshrn_n_s32(temp_low, DCT_CONST_BITS),
vrshrn_n_s32(temp_high, DCT_CONST_BITS));
int32x4_t t[2];
t[0] = vaddl_s16(vget_low_s16(a), vget_low_s16(b));
t[1] = vaddl_s16(vget_high_s16(a), vget_high_s16(b));
t[0] = vmulq_n_s32(t[0], ab_const);
t[1] = vmulq_n_s32(t[1], ab_const);
return dct_const_round_shift_low_8(t);
}
// Subtract b from a, then multiply by ab_const. Shift and narrow by
// DCT_CONST_BITS.
static INLINE int16x8_t sub_multiply_shift_and_narrow_s16(
const int16x8_t a, const int16x8_t b, const int16_t ab_const) {
int32x4_t temp_low = vsubl_s16(vget_low_s16(a), vget_low_s16(b));
int32x4_t temp_high = vsubl_s16(vget_high_s16(a), vget_high_s16(b));
temp_low = vmulq_n_s32(temp_low, ab_const);
temp_high = vmulq_n_s32(temp_high, ab_const);
return vcombine_s16(vrshrn_n_s32(temp_low, DCT_CONST_BITS),
vrshrn_n_s32(temp_high, DCT_CONST_BITS));
int32x4_t t[2];
t[0] = vsubl_s16(vget_low_s16(a), vget_low_s16(b));
t[1] = vsubl_s16(vget_high_s16(a), vget_high_s16(b));
t[0] = vmulq_n_s32(t[0], ab_const);
t[1] = vmulq_n_s32(t[1], ab_const);
return dct_const_round_shift_low_8(t);
}
// Multiply a by a_const and b by b_const, then accumulate. Shift and narrow by
@ -127,12 +149,12 @@ static INLINE int16x8_t sub_multiply_shift_and_narrow_s16(
static INLINE int16x8_t multiply_accumulate_shift_and_narrow_s16(
const int16x8_t a, const int16_t a_const, const int16x8_t b,
const int16_t b_const) {
int32x4_t temp_low = vmull_n_s16(vget_low_s16(a), a_const);
int32x4_t temp_high = vmull_n_s16(vget_high_s16(a), a_const);
temp_low = vmlal_n_s16(temp_low, vget_low_s16(b), b_const);
temp_high = vmlal_n_s16(temp_high, vget_high_s16(b), b_const);
return vcombine_s16(vrshrn_n_s32(temp_low, DCT_CONST_BITS),
vrshrn_n_s32(temp_high, DCT_CONST_BITS));
int32x4_t t[2];
t[0] = vmull_n_s16(vget_low_s16(a), a_const);
t[1] = vmull_n_s16(vget_high_s16(a), a_const);
t[0] = vmlal_n_s16(t[0], vget_low_s16(b), b_const);
t[1] = vmlal_n_s16(t[1], vget_high_s16(b), b_const);
return dct_const_round_shift_low_8(t);
}
//------------------------------------------------------------------------------
@ -145,53 +167,43 @@ static INLINE int16x8_t multiply_accumulate_shift_and_narrow_s16(
static INLINE int32x4x2_t
multiply_shift_and_narrow_s32_dual(const int32x4x2_t a, const int32_t a_const) {
int64x2_t b[4];
int32x4x2_t c;
b[0] = vmull_n_s32(vget_low_s32(a.val[0]), a_const);
b[1] = vmull_n_s32(vget_high_s32(a.val[0]), a_const);
b[2] = vmull_n_s32(vget_low_s32(a.val[1]), a_const);
b[3] = vmull_n_s32(vget_high_s32(a.val[1]), a_const);
c.val[0] = vcombine_s32(vrshrn_n_s64(b[0], DCT_CONST_BITS),
vrshrn_n_s64(b[1], DCT_CONST_BITS));
c.val[1] = vcombine_s32(vrshrn_n_s64(b[2], DCT_CONST_BITS),
vrshrn_n_s64(b[3], DCT_CONST_BITS));
return c;
return dct_const_round_shift_high_4x2(b);
}
// Add a and b, then multiply by ab_const. Shift and narrow by DCT_CONST_BITS.
static INLINE int32x4x2_t add_multiply_shift_and_narrow_s32_dual(
const int32x4x2_t a, const int32x4x2_t b, const int32_t ab_const) {
const int32x4_t temp_low = vaddq_s32(a.val[0], b.val[0]);
const int32x4_t temp_high = vaddq_s32(a.val[1], b.val[1]);
int32x4_t t[2];
int64x2_t c[4];
int32x4x2_t d;
c[0] = vmull_n_s32(vget_low_s32(temp_low), ab_const);
c[1] = vmull_n_s32(vget_high_s32(temp_low), ab_const);
c[2] = vmull_n_s32(vget_low_s32(temp_high), ab_const);
c[3] = vmull_n_s32(vget_high_s32(temp_high), ab_const);
d.val[0] = vcombine_s32(vrshrn_n_s64(c[0], DCT_CONST_BITS),
vrshrn_n_s64(c[1], DCT_CONST_BITS));
d.val[1] = vcombine_s32(vrshrn_n_s64(c[2], DCT_CONST_BITS),
vrshrn_n_s64(c[3], DCT_CONST_BITS));
return d;
t[0] = vaddq_s32(a.val[0], b.val[0]);
t[1] = vaddq_s32(a.val[1], b.val[1]);
c[0] = vmull_n_s32(vget_low_s32(t[0]), ab_const);
c[1] = vmull_n_s32(vget_high_s32(t[0]), ab_const);
c[2] = vmull_n_s32(vget_low_s32(t[1]), ab_const);
c[3] = vmull_n_s32(vget_high_s32(t[1]), ab_const);
return dct_const_round_shift_high_4x2(c);
}
// Subtract b from a, then multiply by ab_const. Shift and narrow by
// DCT_CONST_BITS.
static INLINE int32x4x2_t sub_multiply_shift_and_narrow_s32_dual(
const int32x4x2_t a, const int32x4x2_t b, const int32_t ab_const) {
const int32x4_t temp_low = vsubq_s32(a.val[0], b.val[0]);
const int32x4_t temp_high = vsubq_s32(a.val[1], b.val[1]);
int32x4_t t[2];
int64x2_t c[4];
int32x4x2_t d;
c[0] = vmull_n_s32(vget_low_s32(temp_low), ab_const);
c[1] = vmull_n_s32(vget_high_s32(temp_low), ab_const);
c[2] = vmull_n_s32(vget_low_s32(temp_high), ab_const);
c[3] = vmull_n_s32(vget_high_s32(temp_high), ab_const);
d.val[0] = vcombine_s32(vrshrn_n_s64(c[0], DCT_CONST_BITS),
vrshrn_n_s64(c[1], DCT_CONST_BITS));
d.val[1] = vcombine_s32(vrshrn_n_s64(c[2], DCT_CONST_BITS),
vrshrn_n_s64(c[3], DCT_CONST_BITS));
return d;
t[0] = vsubq_s32(a.val[0], b.val[0]);
t[1] = vsubq_s32(a.val[1], b.val[1]);
c[0] = vmull_n_s32(vget_low_s32(t[0]), ab_const);
c[1] = vmull_n_s32(vget_high_s32(t[0]), ab_const);
c[2] = vmull_n_s32(vget_low_s32(t[1]), ab_const);
c[3] = vmull_n_s32(vget_high_s32(t[1]), ab_const);
return dct_const_round_shift_high_4x2(c);
}
// Multiply a by a_const and b by b_const, then accumulate. Shift and narrow by
@ -200,7 +212,6 @@ static INLINE int32x4x2_t multiply_accumulate_shift_and_narrow_s32_dual(
const int32x4x2_t a, const int32_t a_const, const int32x4x2_t b,
const int32_t b_const) {
int64x2_t c[4];
int32x4x2_t d;
c[0] = vmull_n_s32(vget_low_s32(a.val[0]), a_const);
c[1] = vmull_n_s32(vget_high_s32(a.val[0]), a_const);
c[2] = vmull_n_s32(vget_low_s32(a.val[1]), a_const);
@ -209,11 +220,7 @@ static INLINE int32x4x2_t multiply_accumulate_shift_and_narrow_s32_dual(
c[1] = vmlal_n_s32(c[1], vget_high_s32(b.val[0]), b_const);
c[2] = vmlal_n_s32(c[2], vget_low_s32(b.val[1]), b_const);
c[3] = vmlal_n_s32(c[3], vget_high_s32(b.val[1]), b_const);
d.val[0] = vcombine_s32(vrshrn_n_s64(c[0], DCT_CONST_BITS),
vrshrn_n_s64(c[1], DCT_CONST_BITS));
d.val[1] = vcombine_s32(vrshrn_n_s64(c[2], DCT_CONST_BITS),
vrshrn_n_s64(c[3], DCT_CONST_BITS));
return d;
return dct_const_round_shift_high_4x2(c);
}
// Shift the output down by 6 and add it to the destination buffer.
@ -281,13 +288,12 @@ static INLINE uint8x16_t create_dcq(const int16_t dc) {
return vdupq_n_u8((uint8_t)t);
}
static INLINE void idct4x4_16_kernel_bd8(const int16x4_t cospis,
int16x8_t *const a) {
static INLINE void idct4x4_16_kernel_bd8(int16x8_t *const a) {
const int16x4_t cospis = vld1_s16(kCospi);
int16x4_t b[4];
int32x4_t c[4];
int16x8_t d[2];
transpose_s16_4x4q(&a[0], &a[1]);
b[0] = vget_low_s16(a[0]);
b[1] = vget_high_s16(a[0]);
b[2] = vget_low_s16(a[1]);
@ -296,20 +302,20 @@ static INLINE void idct4x4_16_kernel_bd8(const int16x4_t cospis,
c[2] = vmull_lane_s16(b[1], cospis, 2);
c[1] = vsubq_s32(c[0], c[2]);
c[0] = vaddq_s32(c[0], c[2]);
c[2] = vmull_lane_s16(b[2], cospis, 3);
c[3] = vmull_lane_s16(b[2], cospis, 1);
c[2] = vmlsl_lane_s16(c[2], b[3], cospis, 1);
c[3] = vmlal_lane_s16(c[3], b[3], cospis, 3);
b[0] = vrshrn_n_s32(c[0], DCT_CONST_BITS);
b[1] = vrshrn_n_s32(c[1], DCT_CONST_BITS);
b[2] = vrshrn_n_s32(c[2], DCT_CONST_BITS);
b[3] = vrshrn_n_s32(c[3], DCT_CONST_BITS);
d[0] = vcombine_s16(b[0], b[1]);
d[1] = vcombine_s16(b[3], b[2]);
c[3] = vmull_lane_s16(b[2], cospis, 3);
c[2] = vmull_lane_s16(b[2], cospis, 1);
c[3] = vmlsl_lane_s16(c[3], b[3], cospis, 1);
c[2] = vmlal_lane_s16(c[2], b[3], cospis, 3);
dct_const_round_shift_low_8_dual(c, &d[0], &d[1]);
a[0] = vaddq_s16(d[0], d[1]);
a[1] = vsubq_s16(d[0], d[1]);
}
static INLINE void transpose_idct4x4_16_bd8(int16x8_t *const a) {
transpose_s16_4x4q(&a[0], &a[1]);
idct4x4_16_kernel_bd8(a);
}
static INLINE void idct8x8_12_pass1_bd8(const int16x4_t cospis0,
const int16x4_t cospisd0,
const int16x4_t cospisd1,
@ -366,7 +372,6 @@ static INLINE void idct8x8_12_pass2_bd8(const int16x4_t cospis0,
int16x8_t in[4];
int16x8_t step1[8], step2[8];
int32x4_t t32[8];
int16x4_t t16[8];
transpose_s16_4x8(input[0], input[1], input[2], input[3], input[4], input[5],
input[6], input[7], &in[0], &in[1], &in[2], &in[3]);
@ -399,12 +404,7 @@ static INLINE void idct8x8_12_pass2_bd8(const int16x4_t cospis0,
t32[1] = vmlsl_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
t32[2] = vmlal_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
t32[3] = vmlal_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
t16[0] = vrshrn_n_s32(t32[0], DCT_CONST_BITS);
t16[1] = vrshrn_n_s32(t32[1], DCT_CONST_BITS);
t16[2] = vrshrn_n_s32(t32[2], DCT_CONST_BITS);
t16[3] = vrshrn_n_s32(t32[3], DCT_CONST_BITS);
step1[5] = vcombine_s16(t16[0], t16[1]);
step1[6] = vcombine_s16(t16[2], t16[3]);
dct_const_round_shift_low_8_dual(t32, &step1[5], &step1[6]);
// stage 4
output[0] = vaddq_s16(step1[0], step2[7]);
@ -425,7 +425,6 @@ static INLINE void idct8x8_64_1d_bd8(const int16x4_t cospis0,
int16x4_t step1l[4], step1h[4];
int16x8_t step1[8], step2[8];
int32x4_t t32[8];
int16x4_t t16[8];
transpose_s16_8x8(&io[0], &io[1], &io[2], &io[3], &io[4], &io[5], &io[6],
&io[7]);
@ -464,18 +463,8 @@ static INLINE void idct8x8_64_1d_bd8(const int16x4_t cospis0,
t32[5] = vmlsl_lane_s16(t32[5], input5h, cospis1, 2);
t32[6] = vmlal_lane_s16(t32[6], input7l, cospis1, 3);
t32[7] = vmlal_lane_s16(t32[7], input7h, cospis1, 3);
t16[0] = vrshrn_n_s32(t32[0], DCT_CONST_BITS);
t16[1] = vrshrn_n_s32(t32[1], DCT_CONST_BITS);
t16[2] = vrshrn_n_s32(t32[2], DCT_CONST_BITS);
t16[3] = vrshrn_n_s32(t32[3], DCT_CONST_BITS);
t16[4] = vrshrn_n_s32(t32[4], DCT_CONST_BITS);
t16[5] = vrshrn_n_s32(t32[5], DCT_CONST_BITS);
t16[6] = vrshrn_n_s32(t32[6], DCT_CONST_BITS);
t16[7] = vrshrn_n_s32(t32[7], DCT_CONST_BITS);
step1[4] = vcombine_s16(t16[0], t16[1]);
step1[5] = vcombine_s16(t16[2], t16[3]);
step1[6] = vcombine_s16(t16[4], t16[5]);
step1[7] = vcombine_s16(t16[6], t16[7]);
dct_const_round_shift_low_8_dual(&t32[0], &step1[4], &step1[5]);
dct_const_round_shift_low_8_dual(&t32[4], &step1[6], &step1[7]);
// stage 2
t32[2] = vmull_lane_s16(step1l[0], cospis0, 2);
@ -492,18 +481,8 @@ static INLINE void idct8x8_64_1d_bd8(const int16x4_t cospis0,
t32[5] = vmlsl_lane_s16(t32[5], step1h[3], cospis0, 1);
t32[6] = vmlal_lane_s16(t32[6], step1l[3], cospis0, 3);
t32[7] = vmlal_lane_s16(t32[7], step1h[3], cospis0, 3);
t16[0] = vrshrn_n_s32(t32[0], DCT_CONST_BITS);
t16[1] = vrshrn_n_s32(t32[1], DCT_CONST_BITS);
t16[2] = vrshrn_n_s32(t32[2], DCT_CONST_BITS);
t16[3] = vrshrn_n_s32(t32[3], DCT_CONST_BITS);
t16[4] = vrshrn_n_s32(t32[4], DCT_CONST_BITS);
t16[5] = vrshrn_n_s32(t32[5], DCT_CONST_BITS);
t16[6] = vrshrn_n_s32(t32[6], DCT_CONST_BITS);
t16[7] = vrshrn_n_s32(t32[7], DCT_CONST_BITS);
step2[0] = vcombine_s16(t16[0], t16[1]);
step2[1] = vcombine_s16(t16[2], t16[3]);
step2[2] = vcombine_s16(t16[4], t16[5]);
step2[3] = vcombine_s16(t16[6], t16[7]);
dct_const_round_shift_low_8_dual(&t32[0], &step2[0], &step2[1]);
dct_const_round_shift_low_8_dual(&t32[4], &step2[2], &step2[3]);
step2[4] = vaddq_s16(step1[4], step1[5]);
step2[5] = vsubq_s16(step1[4], step1[5]);
@ -522,12 +501,7 @@ static INLINE void idct8x8_64_1d_bd8(const int16x4_t cospis0,
t32[1] = vmlsl_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
t32[2] = vmlal_lane_s16(t32[2], vget_low_s16(step2[5]), cospis0, 2);
t32[3] = vmlal_lane_s16(t32[3], vget_high_s16(step2[5]), cospis0, 2);
t16[0] = vrshrn_n_s32(t32[0], DCT_CONST_BITS);
t16[1] = vrshrn_n_s32(t32[1], DCT_CONST_BITS);
t16[2] = vrshrn_n_s32(t32[2], DCT_CONST_BITS);
t16[3] = vrshrn_n_s32(t32[3], DCT_CONST_BITS);
step1[5] = vcombine_s16(t16[0], t16[1]);
step1[6] = vcombine_s16(t16[2], t16[3]);
dct_const_round_shift_low_8_dual(t32, &step1[5], &step1[6]);
// stage 4
io[0] = vaddq_s16(step1[0], step2[7]);
@ -540,19 +514,6 @@ static INLINE void idct8x8_64_1d_bd8(const int16x4_t cospis0,
io[7] = vsubq_s16(step1[0], step2[7]);
}
static INLINE void idct16x16_add_wrap_low_8x2(const int32x4_t *const t32,
int16x8_t *const d0,
int16x8_t *const d1) {
int16x4_t t16[4];
t16[0] = vrshrn_n_s32(t32[0], DCT_CONST_BITS);
t16[1] = vrshrn_n_s32(t32[1], DCT_CONST_BITS);
t16[2] = vrshrn_n_s32(t32[2], DCT_CONST_BITS);
t16[3] = vrshrn_n_s32(t32[3], DCT_CONST_BITS);
*d0 = vcombine_s16(t16[0], t16[1]);
*d1 = vcombine_s16(t16[2], t16[3]);
}
static INLINE void idct_cospi_8_24_q_kernel(const int16x8_t s0,
const int16x8_t s1,
const int16x4_t cospi_0_8_16_24,
@ -573,7 +534,7 @@ static INLINE void idct_cospi_8_24_q(const int16x8_t s0, const int16x8_t s1,
int32x4_t t32[4];
idct_cospi_8_24_q_kernel(s0, s1, cospi_0_8_16_24, t32);
idct16x16_add_wrap_low_8x2(t32, d0, d1);
dct_const_round_shift_low_8_dual(t32, d0, d1);
}
static INLINE void idct_cospi_8_24_neg_q(const int16x8_t s0, const int16x8_t s1,
@ -585,7 +546,7 @@ static INLINE void idct_cospi_8_24_neg_q(const int16x8_t s0, const int16x8_t s1,
idct_cospi_8_24_q_kernel(s0, s1, cospi_0_8_16_24, t32);
t32[2] = vnegq_s32(t32[2]);
t32[3] = vnegq_s32(t32[3]);
idct16x16_add_wrap_low_8x2(t32, d0, d1);
dct_const_round_shift_low_8_dual(t32, d0, d1);
}
static INLINE void idct_cospi_16_16_q(const int16x8_t s0, const int16x8_t s1,
@ -600,7 +561,7 @@ static INLINE void idct_cospi_16_16_q(const int16x8_t s0, const int16x8_t s1,
t32[1] = vmlsl_lane_s16(t32[5], vget_high_s16(s0), cospi_0_8_16_24, 2);
t32[2] = vmlal_lane_s16(t32[4], vget_low_s16(s0), cospi_0_8_16_24, 2);
t32[3] = vmlal_lane_s16(t32[5], vget_high_s16(s0), cospi_0_8_16_24, 2);
idct16x16_add_wrap_low_8x2(t32, d0, d1);
dct_const_round_shift_low_8_dual(t32, d0, d1);
}
static INLINE void idct_cospi_2_30(const int16x8_t s0, const int16x8_t s1,
@ -616,7 +577,7 @@ static INLINE void idct_cospi_2_30(const int16x8_t s0, const int16x8_t s1,
t32[1] = vmlsl_lane_s16(t32[1], vget_high_s16(s1), cospi_2_30_10_22, 0);
t32[2] = vmlal_lane_s16(t32[2], vget_low_s16(s0), cospi_2_30_10_22, 0);
t32[3] = vmlal_lane_s16(t32[3], vget_high_s16(s0), cospi_2_30_10_22, 0);
idct16x16_add_wrap_low_8x2(t32, d0, d1);
dct_const_round_shift_low_8_dual(t32, d0, d1);
}
static INLINE void idct_cospi_4_28(const int16x8_t s0, const int16x8_t s1,
@ -632,7 +593,7 @@ static INLINE void idct_cospi_4_28(const int16x8_t s0, const int16x8_t s1,
t32[1] = vmlsl_lane_s16(t32[1], vget_high_s16(s1), cospi_4_12_20N_28, 0);
t32[2] = vmlal_lane_s16(t32[2], vget_low_s16(s0), cospi_4_12_20N_28, 0);
t32[3] = vmlal_lane_s16(t32[3], vget_high_s16(s0), cospi_4_12_20N_28, 0);
idct16x16_add_wrap_low_8x2(t32, d0, d1);
dct_const_round_shift_low_8_dual(t32, d0, d1);
}
static INLINE void idct_cospi_6_26(const int16x8_t s0, const int16x8_t s1,
@ -648,7 +609,7 @@ static INLINE void idct_cospi_6_26(const int16x8_t s0, const int16x8_t s1,
t32[1] = vmlal_lane_s16(t32[1], vget_high_s16(s1), cospi_6_26N_14_18N, 1);
t32[2] = vmlsl_lane_s16(t32[2], vget_low_s16(s0), cospi_6_26N_14_18N, 1);
t32[3] = vmlsl_lane_s16(t32[3], vget_high_s16(s0), cospi_6_26N_14_18N, 1);
idct16x16_add_wrap_low_8x2(t32, d0, d1);
dct_const_round_shift_low_8_dual(t32, d0, d1);
}
static INLINE void idct_cospi_10_22(const int16x8_t s0, const int16x8_t s1,
@ -664,7 +625,7 @@ static INLINE void idct_cospi_10_22(const int16x8_t s0, const int16x8_t s1,
t32[1] = vmlsl_lane_s16(t32[1], vget_high_s16(s1), cospi_2_30_10_22, 2);
t32[2] = vmlal_lane_s16(t32[2], vget_low_s16(s0), cospi_2_30_10_22, 2);
t32[3] = vmlal_lane_s16(t32[3], vget_high_s16(s0), cospi_2_30_10_22, 2);
idct16x16_add_wrap_low_8x2(t32, d0, d1);
dct_const_round_shift_low_8_dual(t32, d0, d1);
}
static INLINE void idct_cospi_12_20(const int16x8_t s0, const int16x8_t s1,
@ -680,7 +641,7 @@ static INLINE void idct_cospi_12_20(const int16x8_t s0, const int16x8_t s1,
t32[1] = vmlal_lane_s16(t32[1], vget_high_s16(s1), cospi_4_12_20N_28, 2);
t32[2] = vmlsl_lane_s16(t32[2], vget_low_s16(s0), cospi_4_12_20N_28, 2);
t32[3] = vmlsl_lane_s16(t32[3], vget_high_s16(s0), cospi_4_12_20N_28, 2);
idct16x16_add_wrap_low_8x2(t32, d0, d1);
dct_const_round_shift_low_8_dual(t32, d0, d1);
}
static INLINE void idct_cospi_14_18(const int16x8_t s0, const int16x8_t s1,
@ -696,7 +657,7 @@ static INLINE void idct_cospi_14_18(const int16x8_t s0, const int16x8_t s1,
t32[1] = vmlal_lane_s16(t32[1], vget_high_s16(s1), cospi_6_26N_14_18N, 3);
t32[2] = vmlsl_lane_s16(t32[2], vget_low_s16(s0), cospi_6_26N_14_18N, 3);
t32[3] = vmlsl_lane_s16(t32[3], vget_high_s16(s0), cospi_6_26N_14_18N, 3);
idct16x16_add_wrap_low_8x2(t32, d0, d1);
dct_const_round_shift_low_8_dual(t32, d0, d1);
}
static INLINE void idct16x16_add_stage7(const int16x8_t *const step2,