Merge "VP8 encoder for ARMv8 by using NEON intrinsics 2"
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Johann
Gerrit Code Review
commit
6642efaa17
@ -456,9 +456,8 @@ $vp8_short_fdct8x4_media=vp8_short_fdct8x4_armv6;
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$vp8_short_fdct8x4_neon_asm=vp8_short_fdct8x4_neon;
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add_proto qw/void vp8_short_walsh4x4/, "short *input, short *output, int pitch";
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specialize qw/vp8_short_walsh4x4 sse2 media neon_asm/;
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specialize qw/vp8_short_walsh4x4 sse2 media neon/;
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$vp8_short_walsh4x4_media=vp8_short_walsh4x4_armv6;
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$vp8_short_walsh4x4_neon_asm=vp8_short_walsh4x4_neon;
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#
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# Quantizer
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@ -1,103 +0,0 @@
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;
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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EXPORT |vp8_short_walsh4x4_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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;void vp8_short_walsh4x4_neon(short *input, short *output, int pitch)
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; r0 short *input,
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; r1 short *output,
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; r2 int pitch
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|vp8_short_walsh4x4_neon| PROC
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vld1.16 {d0}, [r0@64], r2 ; load input
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vld1.16 {d1}, [r0@64], r2
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vld1.16 {d2}, [r0@64], r2
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vld1.16 {d3}, [r0@64]
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;First for-loop
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;transpose d0, d1, d2, d3. Then, d0=ip[0], d1=ip[1], d2=ip[2], d3=ip[3]
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vtrn.32 d0, d2
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vtrn.32 d1, d3
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vmov.s32 q15, #3 ; add 3 to all values
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vtrn.16 d0, d1
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vtrn.16 d2, d3
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vadd.s16 d4, d0, d2 ; ip[0] + ip[2]
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vadd.s16 d5, d1, d3 ; ip[1] + ip[3]
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vsub.s16 d6, d1, d3 ; ip[1] - ip[3]
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vsub.s16 d7, d0, d2 ; ip[0] - ip[2]
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vshl.s16 d4, d4, #2 ; a1 = (ip[0] + ip[2]) << 2
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vshl.s16 d5, d5, #2 ; d1 = (ip[1] + ip[3]) << 2
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vshl.s16 d6, d6, #2 ; c1 = (ip[1] - ip[3]) << 2
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vceq.s16 d16, d4, #0 ; a1 == 0
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vshl.s16 d7, d7, #2 ; b1 = (ip[0] - ip[2]) << 2
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vadd.s16 d0, d4, d5 ; a1 + d1
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vmvn d16, d16 ; a1 != 0
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vsub.s16 d3, d4, d5 ; op[3] = a1 - d1
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vadd.s16 d1, d7, d6 ; op[1] = b1 + c1
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vsub.s16 d2, d7, d6 ; op[2] = b1 - c1
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vsub.s16 d0, d0, d16 ; op[0] = a1 + d1 + (a1 != 0)
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;Second for-loop
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;transpose d0, d1, d2, d3, Then, d0=ip[0], d1=ip[4], d2=ip[8], d3=ip[12]
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vtrn.32 d1, d3
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vtrn.32 d0, d2
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vtrn.16 d2, d3
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vtrn.16 d0, d1
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vaddl.s16 q8, d0, d2 ; a1 = ip[0]+ip[8]
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vaddl.s16 q9, d1, d3 ; d1 = ip[4]+ip[12]
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vsubl.s16 q10, d1, d3 ; c1 = ip[4]-ip[12]
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vsubl.s16 q11, d0, d2 ; b1 = ip[0]-ip[8]
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vadd.s32 q0, q8, q9 ; a2 = a1 + d1
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vadd.s32 q1, q11, q10 ; b2 = b1 + c1
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vsub.s32 q2, q11, q10 ; c2 = b1 - c1
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vsub.s32 q3, q8, q9 ; d2 = a1 - d1
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vclt.s32 q8, q0, #0
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vclt.s32 q9, q1, #0
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vclt.s32 q10, q2, #0
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vclt.s32 q11, q3, #0
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; subtract -1 (or 0)
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vsub.s32 q0, q0, q8 ; a2 += a2 < 0
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vsub.s32 q1, q1, q9 ; b2 += b2 < 0
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vsub.s32 q2, q2, q10 ; c2 += c2 < 0
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vsub.s32 q3, q3, q11 ; d2 += d2 < 0
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vadd.s32 q8, q0, q15 ; a2 + 3
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vadd.s32 q9, q1, q15 ; b2 + 3
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vadd.s32 q10, q2, q15 ; c2 + 3
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vadd.s32 q11, q3, q15 ; d2 + 3
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; vrshrn? would add 1 << 3-1 = 2
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vshrn.s32 d0, q8, #3
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vshrn.s32 d1, q9, #3
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vshrn.s32 d2, q10, #3
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vshrn.s32 d3, q11, #3
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vst1.16 {q0, q1}, [r1@128]
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bx lr
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ENDP
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END
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118
vp8/encoder/arm/neon/vp8_shortwalsh4x4_neon.c
Normal file
118
vp8/encoder/arm/neon/vp8_shortwalsh4x4_neon.c
Normal file
@ -0,0 +1,118 @@
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/*
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* Copyright (c) 2014 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <arm_neon.h>
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void vp8_short_walsh4x4_neon(
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int16_t *input,
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int16_t *output,
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int pitch) {
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uint16x4_t d16u16;
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int16x8_t q0s16, q1s16;
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int16x4_t dEmptys16, d0s16, d1s16, d2s16, d3s16, d4s16, d5s16, d6s16, d7s16;
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int32x4_t qEmptys32, q0s32, q1s32, q2s32, q3s32, q8s32;
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int32x4_t q9s32, q10s32, q11s32, q15s32;
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uint32x4_t q8u32, q9u32, q10u32, q11u32;
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int16x4x2_t v2tmp0, v2tmp1;
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int32x2x2_t v2tmp2, v2tmp3;
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dEmptys16 = vdup_n_s16(0);
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qEmptys32 = vdupq_n_s32(0);
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q15s32 = vdupq_n_s32(3);
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d0s16 = vld1_s16(input);
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input += pitch/2;
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d1s16 = vld1_s16(input);
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input += pitch/2;
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d2s16 = vld1_s16(input);
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input += pitch/2;
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d3s16 = vld1_s16(input);
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v2tmp2 = vtrn_s32(vreinterpret_s32_s16(d0s16),
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vreinterpret_s32_s16(d2s16));
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v2tmp3 = vtrn_s32(vreinterpret_s32_s16(d1s16),
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vreinterpret_s32_s16(d3s16));
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v2tmp0 = vtrn_s16(vreinterpret_s16_s32(v2tmp2.val[0]), // d0
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vreinterpret_s16_s32(v2tmp3.val[0])); // d1
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v2tmp1 = vtrn_s16(vreinterpret_s16_s32(v2tmp2.val[1]), // d2
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vreinterpret_s16_s32(v2tmp3.val[1])); // d3
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d4s16 = vadd_s16(v2tmp0.val[0], v2tmp1.val[0]);
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d5s16 = vadd_s16(v2tmp0.val[1], v2tmp1.val[1]);
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d6s16 = vsub_s16(v2tmp0.val[1], v2tmp1.val[1]);
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d7s16 = vsub_s16(v2tmp0.val[0], v2tmp1.val[0]);
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d4s16 = vshl_n_s16(d4s16, 2);
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d5s16 = vshl_n_s16(d5s16, 2);
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d6s16 = vshl_n_s16(d6s16, 2);
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d7s16 = vshl_n_s16(d7s16, 2);
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d16u16 = vceq_s16(d4s16, dEmptys16);
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d16u16 = vmvn_u16(d16u16);
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d0s16 = vadd_s16(d4s16, d5s16);
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d3s16 = vsub_s16(d4s16, d5s16);
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d1s16 = vadd_s16(d7s16, d6s16);
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d2s16 = vsub_s16(d7s16, d6s16);
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d0s16 = vsub_s16(d0s16, vreinterpret_s16_u16(d16u16));
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// Second for-loop
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v2tmp2 = vtrn_s32(vreinterpret_s32_s16(d1s16),
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vreinterpret_s32_s16(d3s16));
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v2tmp3 = vtrn_s32(vreinterpret_s32_s16(d0s16),
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vreinterpret_s32_s16(d2s16));
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v2tmp0 = vtrn_s16(vreinterpret_s16_s32(v2tmp3.val[1]), // d2
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vreinterpret_s16_s32(v2tmp2.val[1])); // d3
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v2tmp1 = vtrn_s16(vreinterpret_s16_s32(v2tmp3.val[0]), // d0
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vreinterpret_s16_s32(v2tmp2.val[0])); // d1
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q8s32 = vaddl_s16(v2tmp1.val[0], v2tmp0.val[0]);
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q9s32 = vaddl_s16(v2tmp1.val[1], v2tmp0.val[1]);
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q10s32 = vsubl_s16(v2tmp1.val[1], v2tmp0.val[1]);
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q11s32 = vsubl_s16(v2tmp1.val[0], v2tmp0.val[0]);
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q0s32 = vaddq_s32(q8s32, q9s32);
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q1s32 = vaddq_s32(q11s32, q10s32);
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q2s32 = vsubq_s32(q11s32, q10s32);
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q3s32 = vsubq_s32(q8s32, q9s32);
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q8u32 = vcltq_s32(q0s32, qEmptys32);
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q9u32 = vcltq_s32(q1s32, qEmptys32);
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q10u32 = vcltq_s32(q2s32, qEmptys32);
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q11u32 = vcltq_s32(q3s32, qEmptys32);
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q8s32 = vreinterpretq_s32_u32(q8u32);
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q9s32 = vreinterpretq_s32_u32(q9u32);
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q10s32 = vreinterpretq_s32_u32(q10u32);
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q11s32 = vreinterpretq_s32_u32(q11u32);
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q0s32 = vsubq_s32(q0s32, q8s32);
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q1s32 = vsubq_s32(q1s32, q9s32);
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q2s32 = vsubq_s32(q2s32, q10s32);
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q3s32 = vsubq_s32(q3s32, q11s32);
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q8s32 = vaddq_s32(q0s32, q15s32);
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q9s32 = vaddq_s32(q1s32, q15s32);
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q10s32 = vaddq_s32(q2s32, q15s32);
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q11s32 = vaddq_s32(q3s32, q15s32);
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d0s16 = vshrn_n_s32(q8s32, 3);
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d1s16 = vshrn_n_s32(q9s32, 3);
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d2s16 = vshrn_n_s32(q10s32, 3);
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d3s16 = vshrn_n_s32(q11s32, 3);
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q0s16 = vcombine_s16(d0s16, d1s16);
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q1s16 = vcombine_s16(d2s16, d3s16);
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vst1q_s16(output, q0s16);
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vst1q_s16(output + 8, q1s16);
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return;
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}
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@ -41,6 +41,6 @@ VP8_CX_SRCS-$(HAVE_NEON_ASM) += encoder/arm/neon/shortfdct_neon$(ASM)
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VP8_CX_SRCS-$(HAVE_NEON_ASM) += encoder/arm/neon/subtract_neon$(ASM)
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VP8_CX_SRCS-$(HAVE_NEON_ASM) += encoder/arm/neon/vp8_mse16x16_neon$(ASM)
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VP8_CX_SRCS-$(HAVE_NEON_ASM) += encoder/arm/neon/vp8_memcpy_neon$(ASM)
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VP8_CX_SRCS-$(HAVE_NEON_ASM) += encoder/arm/neon/vp8_shortwalsh4x4_neon$(ASM)
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VP8_CX_SRCS-$(HAVE_NEON) += encoder/arm/neon/denoising_neon.c
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VP8_CX_SRCS-$(HAVE_NEON) += encoder/arm/neon/vp8_shortwalsh4x4_neon.c
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