Merge "Add vpx_highbd_idct32x32_135_add_neon()"
This commit is contained in:
James Zern
Gerrit Code Review
commit
2882778310
@ -439,6 +439,15 @@ INSTANTIATE_TEST_CASE_P(C, PartialIDctTest,
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#if HAVE_NEON && !CONFIG_EMULATE_HARDWARE
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const PartialInvTxfmParam neon_partial_idct_tests[] = {
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#if CONFIG_VP9_HIGHBITDEPTH
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make_tuple(
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&vpx_highbd_fdct32x32_c, &highbd_wrapper<vpx_highbd_idct32x32_1024_add_c>,
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&highbd_wrapper<vpx_highbd_idct32x32_135_add_neon>, TX_32X32, 135, 8, 2),
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make_tuple(
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&vpx_highbd_fdct32x32_c, &highbd_wrapper<vpx_highbd_idct32x32_1024_add_c>,
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&highbd_wrapper<vpx_highbd_idct32x32_135_add_neon>, TX_32X32, 135, 10, 2),
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make_tuple(
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&vpx_highbd_fdct32x32_c, &highbd_wrapper<vpx_highbd_idct32x32_1024_add_c>,
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&highbd_wrapper<vpx_highbd_idct32x32_135_add_neon>, TX_32X32, 135, 12, 2),
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make_tuple(
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&vpx_highbd_fdct32x32_c, &highbd_wrapper<vpx_highbd_idct32x32_1024_add_c>,
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&highbd_wrapper<vpx_highbd_idct32x32_1_add_neon>, TX_32X32, 1, 8, 2),
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@ -592,62 +592,6 @@ static INLINE void highbd_idct16x16_store_pass1(const int32x4x2_t *const out,
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vst1q_s32(output + 4, out[15].val[1]);
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}
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static INLINE void highbd_idct16x16_add_store(const int32x4x2_t *const out,
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uint16_t *dest, const int stride,
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const int bd) {
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// Add the result to dest
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const int16x8_t max = vdupq_n_s16((1 << bd) - 1);
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int16x8_t o[16];
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o[0] = vcombine_s16(vrshrn_n_s32(out[0].val[0], 6),
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vrshrn_n_s32(out[0].val[1], 6));
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o[1] = vcombine_s16(vrshrn_n_s32(out[1].val[0], 6),
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vrshrn_n_s32(out[1].val[1], 6));
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o[2] = vcombine_s16(vrshrn_n_s32(out[2].val[0], 6),
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vrshrn_n_s32(out[2].val[1], 6));
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o[3] = vcombine_s16(vrshrn_n_s32(out[3].val[0], 6),
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vrshrn_n_s32(out[3].val[1], 6));
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o[4] = vcombine_s16(vrshrn_n_s32(out[4].val[0], 6),
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vrshrn_n_s32(out[4].val[1], 6));
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o[5] = vcombine_s16(vrshrn_n_s32(out[5].val[0], 6),
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vrshrn_n_s32(out[5].val[1], 6));
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o[6] = vcombine_s16(vrshrn_n_s32(out[6].val[0], 6),
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vrshrn_n_s32(out[6].val[1], 6));
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o[7] = vcombine_s16(vrshrn_n_s32(out[7].val[0], 6),
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vrshrn_n_s32(out[7].val[1], 6));
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o[8] = vcombine_s16(vrshrn_n_s32(out[8].val[0], 6),
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vrshrn_n_s32(out[8].val[1], 6));
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o[9] = vcombine_s16(vrshrn_n_s32(out[9].val[0], 6),
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vrshrn_n_s32(out[9].val[1], 6));
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o[10] = vcombine_s16(vrshrn_n_s32(out[10].val[0], 6),
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vrshrn_n_s32(out[10].val[1], 6));
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o[11] = vcombine_s16(vrshrn_n_s32(out[11].val[0], 6),
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vrshrn_n_s32(out[11].val[1], 6));
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o[12] = vcombine_s16(vrshrn_n_s32(out[12].val[0], 6),
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vrshrn_n_s32(out[12].val[1], 6));
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o[13] = vcombine_s16(vrshrn_n_s32(out[13].val[0], 6),
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vrshrn_n_s32(out[13].val[1], 6));
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o[14] = vcombine_s16(vrshrn_n_s32(out[14].val[0], 6),
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vrshrn_n_s32(out[14].val[1], 6));
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o[15] = vcombine_s16(vrshrn_n_s32(out[15].val[0], 6),
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vrshrn_n_s32(out[15].val[1], 6));
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highbd_idct16x16_add8x1(o[0], max, &dest, stride);
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highbd_idct16x16_add8x1(o[1], max, &dest, stride);
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highbd_idct16x16_add8x1(o[2], max, &dest, stride);
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highbd_idct16x16_add8x1(o[3], max, &dest, stride);
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highbd_idct16x16_add8x1(o[4], max, &dest, stride);
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highbd_idct16x16_add8x1(o[5], max, &dest, stride);
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highbd_idct16x16_add8x1(o[6], max, &dest, stride);
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highbd_idct16x16_add8x1(o[7], max, &dest, stride);
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highbd_idct16x16_add8x1(o[8], max, &dest, stride);
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highbd_idct16x16_add8x1(o[9], max, &dest, stride);
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highbd_idct16x16_add8x1(o[10], max, &dest, stride);
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highbd_idct16x16_add8x1(o[11], max, &dest, stride);
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highbd_idct16x16_add8x1(o[12], max, &dest, stride);
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highbd_idct16x16_add8x1(o[13], max, &dest, stride);
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highbd_idct16x16_add8x1(o[14], max, &dest, stride);
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highbd_idct16x16_add8x1(o[15], max, &dest, stride);
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}
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static void highbd_idct16x16_256_add_half1d(const int32_t *input,
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int32_t *output, uint16_t *dest,
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const int stride, const int bd) {
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@ -902,22 +846,6 @@ static INLINE int32x4_t highbd_idct_cospi_lane1(const int32x4_t s,
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return highbd_idct16x16_add_wrap_low_4x1(t);
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}
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static INLINE int32x4x2_t highbd_idct_add_dual(const int32x4x2_t s0,
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const int32x4x2_t s1) {
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int32x4x2_t t;
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t.val[0] = vaddq_s32(s0.val[0], s1.val[0]);
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t.val[1] = vaddq_s32(s0.val[1], s1.val[1]);
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return t;
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}
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static INLINE int32x4x2_t highbd_idct_sub_dual(const int32x4x2_t s0,
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const int32x4x2_t s1) {
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int32x4x2_t t;
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t.val[0] = vsubq_s32(s0.val[0], s1.val[0]);
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t.val[1] = vsubq_s32(s0.val[1], s1.val[1]);
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return t;
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}
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static void highbd_idct16x16_38_add_half1d(const int32_t *input,
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int32_t *output, uint16_t *dest,
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const int stride, const int bd) {
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757
vpx_dsp/arm/highbd_idct32x32_135_add_neon.c
Normal file
757
vpx_dsp/arm/highbd_idct32x32_135_add_neon.c
Normal file
@ -0,0 +1,757 @@
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/*
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* Copyright (c) 2017 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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#include <arm_neon.h>
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#include "./vpx_config.h"
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#include "./vpx_dsp_rtcd.h"
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#include "vpx_dsp/arm/idct_neon.h"
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#include "vpx_dsp/arm/transpose_neon.h"
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#include "vpx_dsp/txfm_common.h"
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static INLINE void load_8x8_s32_dual(
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const tran_low_t *input, int32x4x2_t *const in0, int32x4x2_t *const in1,
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int32x4x2_t *const in2, int32x4x2_t *const in3, int32x4x2_t *const in4,
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int32x4x2_t *const in5, int32x4x2_t *const in6, int32x4x2_t *const in7) {
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in0->val[0] = vld1q_s32(input);
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in0->val[1] = vld1q_s32(input + 4);
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input += 32;
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in1->val[0] = vld1q_s32(input);
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in1->val[1] = vld1q_s32(input + 4);
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input += 32;
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in2->val[0] = vld1q_s32(input);
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in2->val[1] = vld1q_s32(input + 4);
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input += 32;
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in3->val[0] = vld1q_s32(input);
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in3->val[1] = vld1q_s32(input + 4);
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input += 32;
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in4->val[0] = vld1q_s32(input);
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in4->val[1] = vld1q_s32(input + 4);
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input += 32;
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in5->val[0] = vld1q_s32(input);
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in5->val[1] = vld1q_s32(input + 4);
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input += 32;
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in6->val[0] = vld1q_s32(input);
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in6->val[1] = vld1q_s32(input + 4);
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input += 32;
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in7->val[0] = vld1q_s32(input);
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in7->val[1] = vld1q_s32(input + 4);
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}
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static INLINE void load_4x8_s32_dual(const tran_low_t *input,
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int32x4_t *const in0, int32x4_t *const in1,
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int32x4_t *const in2, int32x4_t *const in3,
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int32x4_t *const in4, int32x4_t *const in5,
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int32x4_t *const in6,
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int32x4_t *const in7) {
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*in0 = vld1q_s32(input);
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input += 32;
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*in1 = vld1q_s32(input);
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input += 32;
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*in2 = vld1q_s32(input);
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input += 32;
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*in3 = vld1q_s32(input);
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input += 32;
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*in4 = vld1q_s32(input);
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input += 32;
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*in5 = vld1q_s32(input);
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input += 32;
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*in6 = vld1q_s32(input);
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input += 32;
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*in7 = vld1q_s32(input);
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}
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// Only for the first pass of the _135_ variant. Since it only uses values from
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// the top left 16x16 it can safely assume all the remaining values are 0 and
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// skip an awful lot of calculations. In fact, only the first 12 columns make
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// the cut. None of the elements in the 13th, 14th, 15th or 16th columns are
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// used so it skips any calls to input[12|13|14|15] too.
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// In C this does a single row of 32 for each call. Here it transposes the top
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// left 12x8 to allow using SIMD.
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// vp9/common/vp9_scan.c:vp9_default_iscan_32x32 arranges the first 135 non-zero
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// coefficients as follows:
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// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
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// 0 0 2 5 10 17 25 38 47 62 83 101 121
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// 1 1 4 8 15 22 30 45 58 74 92 112 133
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// 2 3 7 12 18 28 36 52 64 82 102 118
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// 3 6 11 16 23 31 43 60 73 90 109 126
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// 4 9 14 19 29 37 50 65 78 98 116 134
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// 5 13 20 26 35 44 54 72 85 105 123
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// 6 21 27 33 42 53 63 80 94 113 132
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// 7 24 32 39 48 57 71 88 104 120
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// 8 34 40 46 56 68 81 96 111 130
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// 9 41 49 55 67 77 91 107 124
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// 10 51 59 66 76 89 99 119 131
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// 11 61 69 75 87 100 114 129
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// 12 70 79 86 97 108 122
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// 13 84 93 103 110 125
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// 14 98 106 115 127
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// 15 117 128
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static void highbd_idct32_12_neon(const tran_low_t *const input,
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int32_t *output) {
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int32x4x2_t in[12], s1[32], s2[32], s3[32], s4[32], s5[32], s6[32], s7[32],
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s8[32];
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load_8x8_s32_dual(input, &in[0], &in[1], &in[2], &in[3], &in[4], &in[5],
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&in[6], &in[7]);
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transpose_s32_8x8(&in[0], &in[1], &in[2], &in[3], &in[4], &in[5], &in[6],
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&in[7]);
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load_4x8_s32_dual(input + 8, &in[8].val[0], &in[8].val[1], &in[9].val[0],
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&in[9].val[1], &in[10].val[0], &in[10].val[1],
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&in[11].val[0], &in[11].val[1]);
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transpose_s32_4x8(&in[8].val[0], &in[8].val[1], &in[9].val[0], &in[9].val[1],
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&in[10].val[0], &in[10].val[1], &in[11].val[0],
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&in[11].val[1]);
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// stage 1
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s1[16] = multiply_shift_and_narrow_s32_dual(in[1], cospi_31_64);
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s1[31] = multiply_shift_and_narrow_s32_dual(in[1], cospi_1_64);
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s1[18] = multiply_shift_and_narrow_s32_dual(in[9], cospi_23_64);
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s1[29] = multiply_shift_and_narrow_s32_dual(in[9], cospi_9_64);
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s1[19] = multiply_shift_and_narrow_s32_dual(in[7], -cospi_25_64);
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s1[28] = multiply_shift_and_narrow_s32_dual(in[7], cospi_7_64);
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s1[20] = multiply_shift_and_narrow_s32_dual(in[5], cospi_27_64);
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s1[27] = multiply_shift_and_narrow_s32_dual(in[5], cospi_5_64);
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s1[21] = multiply_shift_and_narrow_s32_dual(in[11], -cospi_21_64);
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s1[26] = multiply_shift_and_narrow_s32_dual(in[11], cospi_11_64);
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s1[23] = multiply_shift_and_narrow_s32_dual(in[3], -cospi_29_64);
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s1[24] = multiply_shift_and_narrow_s32_dual(in[3], cospi_3_64);
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// stage 2
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s2[8] = multiply_shift_and_narrow_s32_dual(in[2], cospi_30_64);
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s2[15] = multiply_shift_and_narrow_s32_dual(in[2], cospi_2_64);
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s2[10] = multiply_shift_and_narrow_s32_dual(in[10], cospi_22_64);
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s2[13] = multiply_shift_and_narrow_s32_dual(in[10], cospi_10_64);
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s2[11] = multiply_shift_and_narrow_s32_dual(in[6], -cospi_26_64);
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s2[12] = multiply_shift_and_narrow_s32_dual(in[6], cospi_6_64);
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s2[18] = highbd_idct_sub_dual(s1[19], s1[18]);
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s2[19] = highbd_idct_add_dual(s1[18], s1[19]);
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s2[20] = highbd_idct_add_dual(s1[20], s1[21]);
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s2[21] = highbd_idct_sub_dual(s1[20], s1[21]);
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s2[26] = highbd_idct_sub_dual(s1[27], s1[26]);
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s2[27] = highbd_idct_add_dual(s1[26], s1[27]);
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s2[28] = highbd_idct_add_dual(s1[28], s1[29]);
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s2[29] = highbd_idct_sub_dual(s1[28], s1[29]);
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// stage 3
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s3[4] = multiply_shift_and_narrow_s32_dual(in[4], cospi_28_64);
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s3[7] = multiply_shift_and_narrow_s32_dual(in[4], cospi_4_64);
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s3[10] = highbd_idct_sub_dual(s2[11], s2[10]);
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s3[11] = highbd_idct_add_dual(s2[10], s2[11]);
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s3[12] = highbd_idct_add_dual(s2[12], s2[13]);
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s3[13] = highbd_idct_sub_dual(s2[12], s2[13]);
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s3[17] = multiply_accumulate_shift_and_narrow_s32_dual(s1[16], -cospi_4_64,
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s1[31], cospi_28_64);
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s3[30] = multiply_accumulate_shift_and_narrow_s32_dual(s1[16], cospi_28_64,
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s1[31], cospi_4_64);
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s3[18] = multiply_accumulate_shift_and_narrow_s32_dual(s2[18], -cospi_28_64,
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s2[29], -cospi_4_64);
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s3[29] = multiply_accumulate_shift_and_narrow_s32_dual(s2[18], -cospi_4_64,
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s2[29], cospi_28_64);
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s3[21] = multiply_accumulate_shift_and_narrow_s32_dual(s2[21], -cospi_20_64,
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s2[26], cospi_12_64);
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s3[26] = multiply_accumulate_shift_and_narrow_s32_dual(s2[21], cospi_12_64,
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s2[26], cospi_20_64);
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s3[22] = multiply_accumulate_shift_and_narrow_s32_dual(s1[23], -cospi_12_64,
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s1[24], -cospi_20_64);
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s3[25] = multiply_accumulate_shift_and_narrow_s32_dual(s1[23], -cospi_20_64,
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s1[24], cospi_12_64);
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// stage 4
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s4[0] = multiply_shift_and_narrow_s32_dual(in[0], cospi_16_64);
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s4[2] = multiply_shift_and_narrow_s32_dual(in[8], cospi_24_64);
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s4[3] = multiply_shift_and_narrow_s32_dual(in[8], cospi_8_64);
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s4[9] = multiply_accumulate_shift_and_narrow_s32_dual(s2[8], -cospi_8_64,
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s2[15], cospi_24_64);
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s4[14] = multiply_accumulate_shift_and_narrow_s32_dual(s2[8], cospi_24_64,
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s2[15], cospi_8_64);
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s4[10] = multiply_accumulate_shift_and_narrow_s32_dual(s3[10], -cospi_24_64,
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s3[13], -cospi_8_64);
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s4[13] = multiply_accumulate_shift_and_narrow_s32_dual(s3[10], -cospi_8_64,
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s3[13], cospi_24_64);
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s4[16] = highbd_idct_add_dual(s1[16], s2[19]);
|
||||
s4[17] = highbd_idct_add_dual(s3[17], s3[18]);
|
||||
s4[18] = highbd_idct_sub_dual(s3[17], s3[18]);
|
||||
s4[19] = highbd_idct_sub_dual(s1[16], s2[19]);
|
||||
s4[20] = highbd_idct_sub_dual(s1[23], s2[20]);
|
||||
s4[21] = highbd_idct_sub_dual(s3[22], s3[21]);
|
||||
s4[22] = highbd_idct_add_dual(s3[21], s3[22]);
|
||||
s4[23] = highbd_idct_add_dual(s2[20], s1[23]);
|
||||
s4[24] = highbd_idct_add_dual(s1[24], s2[27]);
|
||||
s4[25] = highbd_idct_add_dual(s3[25], s3[26]);
|
||||
s4[26] = highbd_idct_sub_dual(s3[25], s3[26]);
|
||||
s4[27] = highbd_idct_sub_dual(s1[24], s2[27]);
|
||||
s4[28] = highbd_idct_sub_dual(s1[31], s2[28]);
|
||||
s4[29] = highbd_idct_sub_dual(s3[30], s3[29]);
|
||||
s4[30] = highbd_idct_add_dual(s3[29], s3[30]);
|
||||
s4[31] = highbd_idct_add_dual(s2[28], s1[31]);
|
||||
|
||||
// stage 5
|
||||
s5[0] = highbd_idct_add_dual(s4[0], s4[3]);
|
||||
s5[1] = highbd_idct_add_dual(s4[0], s4[2]);
|
||||
s5[2] = highbd_idct_sub_dual(s4[0], s4[2]);
|
||||
s5[3] = highbd_idct_sub_dual(s4[0], s4[3]);
|
||||
|
||||
s5[5] = sub_multiply_shift_and_narrow_s32_dual(s3[7], s3[4], cospi_16_64);
|
||||
s5[6] = add_multiply_shift_and_narrow_s32_dual(s3[4], s3[7], cospi_16_64);
|
||||
|
||||
s5[8] = highbd_idct_add_dual(s2[8], s3[11]);
|
||||
s5[9] = highbd_idct_add_dual(s4[9], s4[10]);
|
||||
s5[10] = highbd_idct_sub_dual(s4[9], s4[10]);
|
||||
s5[11] = highbd_idct_sub_dual(s2[8], s3[11]);
|
||||
s5[12] = highbd_idct_sub_dual(s2[15], s3[12]);
|
||||
s5[13] = highbd_idct_sub_dual(s4[14], s4[13]);
|
||||
s5[14] = highbd_idct_add_dual(s4[13], s4[14]);
|
||||
s5[15] = highbd_idct_add_dual(s2[15], s3[12]);
|
||||
|
||||
s5[18] = multiply_accumulate_shift_and_narrow_s32_dual(s4[18], -cospi_8_64,
|
||||
s4[29], cospi_24_64);
|
||||
s5[29] = multiply_accumulate_shift_and_narrow_s32_dual(s4[18], cospi_24_64,
|
||||
s4[29], cospi_8_64);
|
||||
|
||||
s5[19] = multiply_accumulate_shift_and_narrow_s32_dual(s4[19], -cospi_8_64,
|
||||
s4[28], cospi_24_64);
|
||||
s5[28] = multiply_accumulate_shift_and_narrow_s32_dual(s4[19], cospi_24_64,
|
||||
s4[28], cospi_8_64);
|
||||
|
||||
s5[20] = multiply_accumulate_shift_and_narrow_s32_dual(s4[20], -cospi_24_64,
|
||||
s4[27], -cospi_8_64);
|
||||
s5[27] = multiply_accumulate_shift_and_narrow_s32_dual(s4[20], -cospi_8_64,
|
||||
s4[27], cospi_24_64);
|
||||
|
||||
s5[21] = multiply_accumulate_shift_and_narrow_s32_dual(s4[21], -cospi_24_64,
|
||||
s4[26], -cospi_8_64);
|
||||
s5[26] = multiply_accumulate_shift_and_narrow_s32_dual(s4[21], -cospi_8_64,
|
||||
s4[26], cospi_24_64);
|
||||
|
||||
// stage 6
|
||||
s6[0] = highbd_idct_add_dual(s5[0], s3[7]);
|
||||
s6[1] = highbd_idct_add_dual(s5[1], s5[6]);
|
||||
s6[2] = highbd_idct_add_dual(s5[2], s5[5]);
|
||||
s6[3] = highbd_idct_add_dual(s5[3], s3[4]);
|
||||
s6[4] = highbd_idct_sub_dual(s5[3], s3[4]);
|
||||
s6[5] = highbd_idct_sub_dual(s5[2], s5[5]);
|
||||
s6[6] = highbd_idct_sub_dual(s5[1], s5[6]);
|
||||
s6[7] = highbd_idct_sub_dual(s5[0], s3[7]);
|
||||
|
||||
s6[10] = sub_multiply_shift_and_narrow_s32_dual(s5[13], s5[10], cospi_16_64);
|
||||
s6[13] = add_multiply_shift_and_narrow_s32_dual(s5[10], s5[13], cospi_16_64);
|
||||
|
||||
s6[11] = sub_multiply_shift_and_narrow_s32_dual(s5[12], s5[11], cospi_16_64);
|
||||
s6[12] = add_multiply_shift_and_narrow_s32_dual(s5[11], s5[12], cospi_16_64);
|
||||
|
||||
s6[16] = highbd_idct_add_dual(s4[16], s4[23]);
|
||||
s6[17] = highbd_idct_add_dual(s4[17], s4[22]);
|
||||
s6[18] = highbd_idct_add_dual(s5[18], s5[21]);
|
||||
s6[19] = highbd_idct_add_dual(s5[19], s5[20]);
|
||||
s6[20] = highbd_idct_sub_dual(s5[19], s5[20]);
|
||||
s6[21] = highbd_idct_sub_dual(s5[18], s5[21]);
|
||||
s6[22] = highbd_idct_sub_dual(s4[17], s4[22]);
|
||||
s6[23] = highbd_idct_sub_dual(s4[16], s4[23]);
|
||||
|
||||
s6[24] = highbd_idct_sub_dual(s4[31], s4[24]);
|
||||
s6[25] = highbd_idct_sub_dual(s4[30], s4[25]);
|
||||
s6[26] = highbd_idct_sub_dual(s5[29], s5[26]);
|
||||
s6[27] = highbd_idct_sub_dual(s5[28], s5[27]);
|
||||
s6[28] = highbd_idct_add_dual(s5[27], s5[28]);
|
||||
s6[29] = highbd_idct_add_dual(s5[26], s5[29]);
|
||||
s6[30] = highbd_idct_add_dual(s4[25], s4[30]);
|
||||
s6[31] = highbd_idct_add_dual(s4[24], s4[31]);
|
||||
|
||||
// stage 7
|
||||
s7[0] = highbd_idct_add_dual(s6[0], s5[15]);
|
||||
s7[1] = highbd_idct_add_dual(s6[1], s5[14]);
|
||||
s7[2] = highbd_idct_add_dual(s6[2], s6[13]);
|
||||
s7[3] = highbd_idct_add_dual(s6[3], s6[12]);
|
||||
s7[4] = highbd_idct_add_dual(s6[4], s6[11]);
|
||||
s7[5] = highbd_idct_add_dual(s6[5], s6[10]);
|
||||
s7[6] = highbd_idct_add_dual(s6[6], s5[9]);
|
||||
s7[7] = highbd_idct_add_dual(s6[7], s5[8]);
|
||||
s7[8] = highbd_idct_sub_dual(s6[7], s5[8]);
|
||||
s7[9] = highbd_idct_sub_dual(s6[6], s5[9]);
|
||||
s7[10] = highbd_idct_sub_dual(s6[5], s6[10]);
|
||||
s7[11] = highbd_idct_sub_dual(s6[4], s6[11]);
|
||||
s7[12] = highbd_idct_sub_dual(s6[3], s6[12]);
|
||||
s7[13] = highbd_idct_sub_dual(s6[2], s6[13]);
|
||||
s7[14] = highbd_idct_sub_dual(s6[1], s5[14]);
|
||||
s7[15] = highbd_idct_sub_dual(s6[0], s5[15]);
|
||||
|
||||
s7[20] = sub_multiply_shift_and_narrow_s32_dual(s6[27], s6[20], cospi_16_64);
|
||||
s7[27] = add_multiply_shift_and_narrow_s32_dual(s6[20], s6[27], cospi_16_64);
|
||||
|
||||
s7[21] = sub_multiply_shift_and_narrow_s32_dual(s6[26], s6[21], cospi_16_64);
|
||||
s7[26] = add_multiply_shift_and_narrow_s32_dual(s6[21], s6[26], cospi_16_64);
|
||||
|
||||
s7[22] = sub_multiply_shift_and_narrow_s32_dual(s6[25], s6[22], cospi_16_64);
|
||||
s7[25] = add_multiply_shift_and_narrow_s32_dual(s6[22], s6[25], cospi_16_64);
|
||||
|
||||
s7[23] = sub_multiply_shift_and_narrow_s32_dual(s6[24], s6[23], cospi_16_64);
|
||||
s7[24] = add_multiply_shift_and_narrow_s32_dual(s6[23], s6[24], cospi_16_64);
|
||||
|
||||
// final stage
|
||||
s8[0] = highbd_idct_add_dual(s7[0], s6[31]);
|
||||
s8[1] = highbd_idct_add_dual(s7[1], s6[30]);
|
||||
s8[2] = highbd_idct_add_dual(s7[2], s6[29]);
|
||||
s8[3] = highbd_idct_add_dual(s7[3], s6[28]);
|
||||
s8[4] = highbd_idct_add_dual(s7[4], s7[27]);
|
||||
s8[5] = highbd_idct_add_dual(s7[5], s7[26]);
|
||||
s8[6] = highbd_idct_add_dual(s7[6], s7[25]);
|
||||
s8[7] = highbd_idct_add_dual(s7[7], s7[24]);
|
||||
s8[8] = highbd_idct_add_dual(s7[8], s7[23]);
|
||||
s8[9] = highbd_idct_add_dual(s7[9], s7[22]);
|
||||
s8[10] = highbd_idct_add_dual(s7[10], s7[21]);
|
||||
s8[11] = highbd_idct_add_dual(s7[11], s7[20]);
|
||||
s8[12] = highbd_idct_add_dual(s7[12], s6[19]);
|
||||
s8[13] = highbd_idct_add_dual(s7[13], s6[18]);
|
||||
s8[14] = highbd_idct_add_dual(s7[14], s6[17]);
|
||||
s8[15] = highbd_idct_add_dual(s7[15], s6[16]);
|
||||
s8[16] = highbd_idct_sub_dual(s7[15], s6[16]);
|
||||
s8[17] = highbd_idct_sub_dual(s7[14], s6[17]);
|
||||
s8[18] = highbd_idct_sub_dual(s7[13], s6[18]);
|
||||
s8[19] = highbd_idct_sub_dual(s7[12], s6[19]);
|
||||
s8[20] = highbd_idct_sub_dual(s7[11], s7[20]);
|
||||
s8[21] = highbd_idct_sub_dual(s7[10], s7[21]);
|
||||
s8[22] = highbd_idct_sub_dual(s7[9], s7[22]);
|
||||
s8[23] = highbd_idct_sub_dual(s7[8], s7[23]);
|
||||
s8[24] = highbd_idct_sub_dual(s7[7], s7[24]);
|
||||
s8[25] = highbd_idct_sub_dual(s7[6], s7[25]);
|
||||
s8[26] = highbd_idct_sub_dual(s7[5], s7[26]);
|
||||
s8[27] = highbd_idct_sub_dual(s7[4], s7[27]);
|
||||
s8[28] = highbd_idct_sub_dual(s7[3], s6[28]);
|
||||
s8[29] = highbd_idct_sub_dual(s7[2], s6[29]);
|
||||
s8[30] = highbd_idct_sub_dual(s7[1], s6[30]);
|
||||
s8[31] = highbd_idct_sub_dual(s7[0], s6[31]);
|
||||
|
||||
vst1q_s32(output + 0, s8[0].val[0]);
|
||||
vst1q_s32(output + 4, s8[0].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[1].val[0]);
|
||||
vst1q_s32(output + 4, s8[1].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[2].val[0]);
|
||||
vst1q_s32(output + 4, s8[2].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[3].val[0]);
|
||||
vst1q_s32(output + 4, s8[3].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[4].val[0]);
|
||||
vst1q_s32(output + 4, s8[4].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[5].val[0]);
|
||||
vst1q_s32(output + 4, s8[5].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[6].val[0]);
|
||||
vst1q_s32(output + 4, s8[6].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[7].val[0]);
|
||||
vst1q_s32(output + 4, s8[7].val[1]);
|
||||
output += 16;
|
||||
|
||||
vst1q_s32(output + 0, s8[8].val[0]);
|
||||
vst1q_s32(output + 4, s8[8].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[9].val[0]);
|
||||
vst1q_s32(output + 4, s8[9].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[10].val[0]);
|
||||
vst1q_s32(output + 4, s8[10].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[11].val[0]);
|
||||
vst1q_s32(output + 4, s8[11].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[12].val[0]);
|
||||
vst1q_s32(output + 4, s8[12].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[13].val[0]);
|
||||
vst1q_s32(output + 4, s8[13].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[14].val[0]);
|
||||
vst1q_s32(output + 4, s8[14].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[15].val[0]);
|
||||
vst1q_s32(output + 4, s8[15].val[1]);
|
||||
output += 16;
|
||||
|
||||
vst1q_s32(output + 0, s8[16].val[0]);
|
||||
vst1q_s32(output + 4, s8[16].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[17].val[0]);
|
||||
vst1q_s32(output + 4, s8[17].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[18].val[0]);
|
||||
vst1q_s32(output + 4, s8[18].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[19].val[0]);
|
||||
vst1q_s32(output + 4, s8[19].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[20].val[0]);
|
||||
vst1q_s32(output + 4, s8[20].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[21].val[0]);
|
||||
vst1q_s32(output + 4, s8[21].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[22].val[0]);
|
||||
vst1q_s32(output + 4, s8[22].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[23].val[0]);
|
||||
vst1q_s32(output + 4, s8[23].val[1]);
|
||||
output += 16;
|
||||
|
||||
vst1q_s32(output + 0, s8[24].val[0]);
|
||||
vst1q_s32(output + 4, s8[24].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[25].val[0]);
|
||||
vst1q_s32(output + 4, s8[25].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[26].val[0]);
|
||||
vst1q_s32(output + 4, s8[26].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[27].val[0]);
|
||||
vst1q_s32(output + 4, s8[27].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[28].val[0]);
|
||||
vst1q_s32(output + 4, s8[28].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[29].val[0]);
|
||||
vst1q_s32(output + 4, s8[29].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[30].val[0]);
|
||||
vst1q_s32(output + 4, s8[30].val[1]);
|
||||
output += 16;
|
||||
vst1q_s32(output + 0, s8[31].val[0]);
|
||||
vst1q_s32(output + 4, s8[31].val[1]);
|
||||
}
|
||||
|
||||
static void highbd_idct32_16_neon(const int32_t *const input,
|
||||
uint16_t *const output, const int stride,
|
||||
const int bd) {
|
||||
int32x4x2_t in[16], s1[32], s2[32], s3[32], s4[32], s5[32], s6[32], s7[32],
|
||||
out[32];
|
||||
|
||||
load_and_transpose_s32_8x8(input, 16, &in[0], &in[1], &in[2], &in[3], &in[4],
|
||||
&in[5], &in[6], &in[7]);
|
||||
|
||||
load_and_transpose_s32_8x8(input + 8, 16, &in[8], &in[9], &in[10], &in[11],
|
||||
&in[12], &in[13], &in[14], &in[15]);
|
||||
|
||||
// stage 1
|
||||
s1[16] = multiply_shift_and_narrow_s32_dual(in[1], cospi_31_64);
|
||||
s1[31] = multiply_shift_and_narrow_s32_dual(in[1], cospi_1_64);
|
||||
|
||||
s1[17] = multiply_shift_and_narrow_s32_dual(in[15], -cospi_17_64);
|
||||
s1[30] = multiply_shift_and_narrow_s32_dual(in[15], cospi_15_64);
|
||||
|
||||
s1[18] = multiply_shift_and_narrow_s32_dual(in[9], cospi_23_64);
|
||||
s1[29] = multiply_shift_and_narrow_s32_dual(in[9], cospi_9_64);
|
||||
|
||||
s1[19] = multiply_shift_and_narrow_s32_dual(in[7], -cospi_25_64);
|
||||
s1[28] = multiply_shift_and_narrow_s32_dual(in[7], cospi_7_64);
|
||||
|
||||
s1[20] = multiply_shift_and_narrow_s32_dual(in[5], cospi_27_64);
|
||||
s1[27] = multiply_shift_and_narrow_s32_dual(in[5], cospi_5_64);
|
||||
|
||||
s1[21] = multiply_shift_and_narrow_s32_dual(in[11], -cospi_21_64);
|
||||
s1[26] = multiply_shift_and_narrow_s32_dual(in[11], cospi_11_64);
|
||||
|
||||
s1[22] = multiply_shift_and_narrow_s32_dual(in[13], cospi_19_64);
|
||||
s1[25] = multiply_shift_and_narrow_s32_dual(in[13], cospi_13_64);
|
||||
|
||||
s1[23] = multiply_shift_and_narrow_s32_dual(in[3], -cospi_29_64);
|
||||
s1[24] = multiply_shift_and_narrow_s32_dual(in[3], cospi_3_64);
|
||||
|
||||
// stage 2
|
||||
s2[8] = multiply_shift_and_narrow_s32_dual(in[2], cospi_30_64);
|
||||
s2[15] = multiply_shift_and_narrow_s32_dual(in[2], cospi_2_64);
|
||||
|
||||
s2[9] = multiply_shift_and_narrow_s32_dual(in[14], -cospi_18_64);
|
||||
s2[14] = multiply_shift_and_narrow_s32_dual(in[14], cospi_14_64);
|
||||
|
||||
s2[10] = multiply_shift_and_narrow_s32_dual(in[10], cospi_22_64);
|
||||
s2[13] = multiply_shift_and_narrow_s32_dual(in[10], cospi_10_64);
|
||||
|
||||
s2[11] = multiply_shift_and_narrow_s32_dual(in[6], -cospi_26_64);
|
||||
s2[12] = multiply_shift_and_narrow_s32_dual(in[6], cospi_6_64);
|
||||
|
||||
s2[16] = highbd_idct_add_dual(s1[16], s1[17]);
|
||||
s2[17] = highbd_idct_sub_dual(s1[16], s1[17]);
|
||||
s2[18] = highbd_idct_sub_dual(s1[19], s1[18]);
|
||||
s2[19] = highbd_idct_add_dual(s1[18], s1[19]);
|
||||
s2[20] = highbd_idct_add_dual(s1[20], s1[21]);
|
||||
s2[21] = highbd_idct_sub_dual(s1[20], s1[21]);
|
||||
s2[22] = highbd_idct_sub_dual(s1[23], s1[22]);
|
||||
s2[23] = highbd_idct_add_dual(s1[22], s1[23]);
|
||||
s2[24] = highbd_idct_add_dual(s1[24], s1[25]);
|
||||
s2[25] = highbd_idct_sub_dual(s1[24], s1[25]);
|
||||
s2[26] = highbd_idct_sub_dual(s1[27], s1[26]);
|
||||
s2[27] = highbd_idct_add_dual(s1[26], s1[27]);
|
||||
s2[28] = highbd_idct_add_dual(s1[28], s1[29]);
|
||||
s2[29] = highbd_idct_sub_dual(s1[28], s1[29]);
|
||||
s2[30] = highbd_idct_sub_dual(s1[31], s1[30]);
|
||||
s2[31] = highbd_idct_add_dual(s1[30], s1[31]);
|
||||
|
||||
// stage 3
|
||||
s3[4] = multiply_shift_and_narrow_s32_dual(in[4], cospi_28_64);
|
||||
s3[7] = multiply_shift_and_narrow_s32_dual(in[4], cospi_4_64);
|
||||
|
||||
s3[5] = multiply_shift_and_narrow_s32_dual(in[12], -cospi_20_64);
|
||||
s3[6] = multiply_shift_and_narrow_s32_dual(in[12], cospi_12_64);
|
||||
|
||||
s3[8] = highbd_idct_add_dual(s2[8], s2[9]);
|
||||
s3[9] = highbd_idct_sub_dual(s2[8], s2[9]);
|
||||
s3[10] = highbd_idct_sub_dual(s2[11], s2[10]);
|
||||
s3[11] = highbd_idct_add_dual(s2[10], s2[11]);
|
||||
s3[12] = highbd_idct_add_dual(s2[12], s2[13]);
|
||||
s3[13] = highbd_idct_sub_dual(s2[12], s2[13]);
|
||||
s3[14] = highbd_idct_sub_dual(s2[15], s2[14]);
|
||||
s3[15] = highbd_idct_add_dual(s2[14], s2[15]);
|
||||
|
||||
s3[17] = multiply_accumulate_shift_and_narrow_s32_dual(s2[17], -cospi_4_64,
|
||||
s2[30], cospi_28_64);
|
||||
s3[30] = multiply_accumulate_shift_and_narrow_s32_dual(s2[17], cospi_28_64,
|
||||
s2[30], cospi_4_64);
|
||||
|
||||
s3[18] = multiply_accumulate_shift_and_narrow_s32_dual(s2[18], -cospi_28_64,
|
||||
s2[29], -cospi_4_64);
|
||||
s3[29] = multiply_accumulate_shift_and_narrow_s32_dual(s2[18], -cospi_4_64,
|
||||
s2[29], cospi_28_64);
|
||||
|
||||
s3[21] = multiply_accumulate_shift_and_narrow_s32_dual(s2[21], -cospi_20_64,
|
||||
s2[26], cospi_12_64);
|
||||
s3[26] = multiply_accumulate_shift_and_narrow_s32_dual(s2[21], cospi_12_64,
|
||||
s2[26], cospi_20_64);
|
||||
|
||||
s3[22] = multiply_accumulate_shift_and_narrow_s32_dual(s2[22], -cospi_12_64,
|
||||
s2[25], -cospi_20_64);
|
||||
s3[25] = multiply_accumulate_shift_and_narrow_s32_dual(s2[22], -cospi_20_64,
|
||||
s2[25], cospi_12_64);
|
||||
|
||||
// stage 4
|
||||
s4[0] = multiply_shift_and_narrow_s32_dual(in[0], cospi_16_64);
|
||||
s4[2] = multiply_shift_and_narrow_s32_dual(in[8], cospi_24_64);
|
||||
s4[3] = multiply_shift_and_narrow_s32_dual(in[8], cospi_8_64);
|
||||
|
||||
s4[4] = highbd_idct_add_dual(s3[4], s3[5]);
|
||||
s4[5] = highbd_idct_sub_dual(s3[4], s3[5]);
|
||||
s4[6] = highbd_idct_sub_dual(s3[7], s3[6]);
|
||||
s4[7] = highbd_idct_add_dual(s3[6], s3[7]);
|
||||
|
||||
s4[9] = multiply_accumulate_shift_and_narrow_s32_dual(s3[9], -cospi_8_64,
|
||||
s3[14], cospi_24_64);
|
||||
s4[14] = multiply_accumulate_shift_and_narrow_s32_dual(s3[9], cospi_24_64,
|
||||
s3[14], cospi_8_64);
|
||||
|
||||
s4[10] = multiply_accumulate_shift_and_narrow_s32_dual(s3[10], -cospi_24_64,
|
||||
s3[13], -cospi_8_64);
|
||||
s4[13] = multiply_accumulate_shift_and_narrow_s32_dual(s3[10], -cospi_8_64,
|
||||
s3[13], cospi_24_64);
|
||||
|
||||
s4[16] = highbd_idct_add_dual(s2[16], s2[19]);
|
||||
s4[17] = highbd_idct_add_dual(s3[17], s3[18]);
|
||||
s4[18] = highbd_idct_sub_dual(s3[17], s3[18]);
|
||||
s4[19] = highbd_idct_sub_dual(s2[16], s2[19]);
|
||||
s4[20] = highbd_idct_sub_dual(s2[23], s2[20]);
|
||||
s4[21] = highbd_idct_sub_dual(s3[22], s3[21]);
|
||||
s4[22] = highbd_idct_add_dual(s3[21], s3[22]);
|
||||
s4[23] = highbd_idct_add_dual(s2[20], s2[23]);
|
||||
s4[24] = highbd_idct_add_dual(s2[24], s2[27]);
|
||||
s4[25] = highbd_idct_add_dual(s3[25], s3[26]);
|
||||
s4[26] = highbd_idct_sub_dual(s3[25], s3[26]);
|
||||
s4[27] = highbd_idct_sub_dual(s2[24], s2[27]);
|
||||
s4[28] = highbd_idct_sub_dual(s2[31], s2[28]);
|
||||
s4[29] = highbd_idct_sub_dual(s3[30], s3[29]);
|
||||
s4[30] = highbd_idct_add_dual(s3[29], s3[30]);
|
||||
s4[31] = highbd_idct_add_dual(s2[28], s2[31]);
|
||||
|
||||
// stage 5
|
||||
s5[0] = highbd_idct_add_dual(s4[0], s4[3]);
|
||||
s5[1] = highbd_idct_add_dual(s4[0], s4[2]);
|
||||
s5[2] = highbd_idct_sub_dual(s4[0], s4[2]);
|
||||
s5[3] = highbd_idct_sub_dual(s4[0], s4[3]);
|
||||
|
||||
s5[5] = sub_multiply_shift_and_narrow_s32_dual(s4[6], s4[5], cospi_16_64);
|
||||
s5[6] = add_multiply_shift_and_narrow_s32_dual(s4[5], s4[6], cospi_16_64);
|
||||
|
||||
s5[8] = highbd_idct_add_dual(s3[8], s3[11]);
|
||||
s5[9] = highbd_idct_add_dual(s4[9], s4[10]);
|
||||
s5[10] = highbd_idct_sub_dual(s4[9], s4[10]);
|
||||
s5[11] = highbd_idct_sub_dual(s3[8], s3[11]);
|
||||
s5[12] = highbd_idct_sub_dual(s3[15], s3[12]);
|
||||
s5[13] = highbd_idct_sub_dual(s4[14], s4[13]);
|
||||
s5[14] = highbd_idct_add_dual(s4[13], s4[14]);
|
||||
s5[15] = highbd_idct_add_dual(s3[15], s3[12]);
|
||||
|
||||
s5[18] = multiply_accumulate_shift_and_narrow_s32_dual(s4[18], -cospi_8_64,
|
||||
s4[29], cospi_24_64);
|
||||
s5[29] = multiply_accumulate_shift_and_narrow_s32_dual(s4[18], cospi_24_64,
|
||||
s4[29], cospi_8_64);
|
||||
|
||||
s5[19] = multiply_accumulate_shift_and_narrow_s32_dual(s4[19], -cospi_8_64,
|
||||
s4[28], cospi_24_64);
|
||||
s5[28] = multiply_accumulate_shift_and_narrow_s32_dual(s4[19], cospi_24_64,
|
||||
s4[28], cospi_8_64);
|
||||
|
||||
s5[20] = multiply_accumulate_shift_and_narrow_s32_dual(s4[20], -cospi_24_64,
|
||||
s4[27], -cospi_8_64);
|
||||
s5[27] = multiply_accumulate_shift_and_narrow_s32_dual(s4[20], -cospi_8_64,
|
||||
s4[27], cospi_24_64);
|
||||
|
||||
s5[21] = multiply_accumulate_shift_and_narrow_s32_dual(s4[21], -cospi_24_64,
|
||||
s4[26], -cospi_8_64);
|
||||
s5[26] = multiply_accumulate_shift_and_narrow_s32_dual(s4[21], -cospi_8_64,
|
||||
s4[26], cospi_24_64);
|
||||
|
||||
// stage 6
|
||||
s6[0] = highbd_idct_add_dual(s5[0], s4[7]);
|
||||
s6[1] = highbd_idct_add_dual(s5[1], s5[6]);
|
||||
s6[2] = highbd_idct_add_dual(s5[2], s5[5]);
|
||||
s6[3] = highbd_idct_add_dual(s5[3], s4[4]);
|
||||
s6[4] = highbd_idct_sub_dual(s5[3], s4[4]);
|
||||
s6[5] = highbd_idct_sub_dual(s5[2], s5[5]);
|
||||
s6[6] = highbd_idct_sub_dual(s5[1], s5[6]);
|
||||
s6[7] = highbd_idct_sub_dual(s5[0], s4[7]);
|
||||
|
||||
s6[10] = sub_multiply_shift_and_narrow_s32_dual(s5[13], s5[10], cospi_16_64);
|
||||
s6[13] = add_multiply_shift_and_narrow_s32_dual(s5[10], s5[13], cospi_16_64);
|
||||
|
||||
s6[11] = sub_multiply_shift_and_narrow_s32_dual(s5[12], s5[11], cospi_16_64);
|
||||
s6[12] = add_multiply_shift_and_narrow_s32_dual(s5[11], s5[12], cospi_16_64);
|
||||
|
||||
s6[16] = highbd_idct_add_dual(s4[16], s4[23]);
|
||||
s6[17] = highbd_idct_add_dual(s4[17], s4[22]);
|
||||
s6[18] = highbd_idct_add_dual(s5[18], s5[21]);
|
||||
s6[19] = highbd_idct_add_dual(s5[19], s5[20]);
|
||||
s6[20] = highbd_idct_sub_dual(s5[19], s5[20]);
|
||||
s6[21] = highbd_idct_sub_dual(s5[18], s5[21]);
|
||||
s6[22] = highbd_idct_sub_dual(s4[17], s4[22]);
|
||||
s6[23] = highbd_idct_sub_dual(s4[16], s4[23]);
|
||||
s6[24] = highbd_idct_sub_dual(s4[31], s4[24]);
|
||||
s6[25] = highbd_idct_sub_dual(s4[30], s4[25]);
|
||||
s6[26] = highbd_idct_sub_dual(s5[29], s5[26]);
|
||||
s6[27] = highbd_idct_sub_dual(s5[28], s5[27]);
|
||||
s6[28] = highbd_idct_add_dual(s5[27], s5[28]);
|
||||
s6[29] = highbd_idct_add_dual(s5[26], s5[29]);
|
||||
s6[30] = highbd_idct_add_dual(s4[25], s4[30]);
|
||||
s6[31] = highbd_idct_add_dual(s4[24], s4[31]);
|
||||
|
||||
// stage 7
|
||||
s7[0] = highbd_idct_add_dual(s6[0], s5[15]);
|
||||
s7[1] = highbd_idct_add_dual(s6[1], s5[14]);
|
||||
s7[2] = highbd_idct_add_dual(s6[2], s6[13]);
|
||||
s7[3] = highbd_idct_add_dual(s6[3], s6[12]);
|
||||
s7[4] = highbd_idct_add_dual(s6[4], s6[11]);
|
||||
s7[5] = highbd_idct_add_dual(s6[5], s6[10]);
|
||||
s7[6] = highbd_idct_add_dual(s6[6], s5[9]);
|
||||
s7[7] = highbd_idct_add_dual(s6[7], s5[8]);
|
||||
s7[8] = highbd_idct_sub_dual(s6[7], s5[8]);
|
||||
s7[9] = highbd_idct_sub_dual(s6[6], s5[9]);
|
||||
s7[10] = highbd_idct_sub_dual(s6[5], s6[10]);
|
||||
s7[11] = highbd_idct_sub_dual(s6[4], s6[11]);
|
||||
s7[12] = highbd_idct_sub_dual(s6[3], s6[12]);
|
||||
s7[13] = highbd_idct_sub_dual(s6[2], s6[13]);
|
||||
s7[14] = highbd_idct_sub_dual(s6[1], s5[14]);
|
||||
s7[15] = highbd_idct_sub_dual(s6[0], s5[15]);
|
||||
|
||||
s7[20] = sub_multiply_shift_and_narrow_s32_dual(s6[27], s6[20], cospi_16_64);
|
||||
s7[27] = add_multiply_shift_and_narrow_s32_dual(s6[20], s6[27], cospi_16_64);
|
||||
|
||||
s7[21] = sub_multiply_shift_and_narrow_s32_dual(s6[26], s6[21], cospi_16_64);
|
||||
s7[26] = add_multiply_shift_and_narrow_s32_dual(s6[21], s6[26], cospi_16_64);
|
||||
|
||||
s7[22] = sub_multiply_shift_and_narrow_s32_dual(s6[25], s6[22], cospi_16_64);
|
||||
s7[25] = add_multiply_shift_and_narrow_s32_dual(s6[22], s6[25], cospi_16_64);
|
||||
|
||||
s7[23] = sub_multiply_shift_and_narrow_s32_dual(s6[24], s6[23], cospi_16_64);
|
||||
s7[24] = add_multiply_shift_and_narrow_s32_dual(s6[23], s6[24], cospi_16_64);
|
||||
|
||||
// final stage
|
||||
out[0] = highbd_idct_add_dual(s7[0], s6[31]);
|
||||
out[1] = highbd_idct_add_dual(s7[1], s6[30]);
|
||||
out[2] = highbd_idct_add_dual(s7[2], s6[29]);
|
||||
out[3] = highbd_idct_add_dual(s7[3], s6[28]);
|
||||
out[4] = highbd_idct_add_dual(s7[4], s7[27]);
|
||||
out[5] = highbd_idct_add_dual(s7[5], s7[26]);
|
||||
out[6] = highbd_idct_add_dual(s7[6], s7[25]);
|
||||
out[7] = highbd_idct_add_dual(s7[7], s7[24]);
|
||||
out[8] = highbd_idct_add_dual(s7[8], s7[23]);
|
||||
out[9] = highbd_idct_add_dual(s7[9], s7[22]);
|
||||
out[10] = highbd_idct_add_dual(s7[10], s7[21]);
|
||||
out[11] = highbd_idct_add_dual(s7[11], s7[20]);
|
||||
out[12] = highbd_idct_add_dual(s7[12], s6[19]);
|
||||
out[13] = highbd_idct_add_dual(s7[13], s6[18]);
|
||||
out[14] = highbd_idct_add_dual(s7[14], s6[17]);
|
||||
out[15] = highbd_idct_add_dual(s7[15], s6[16]);
|
||||
out[16] = highbd_idct_sub_dual(s7[15], s6[16]);
|
||||
out[17] = highbd_idct_sub_dual(s7[14], s6[17]);
|
||||
out[18] = highbd_idct_sub_dual(s7[13], s6[18]);
|
||||
out[19] = highbd_idct_sub_dual(s7[12], s6[19]);
|
||||
out[20] = highbd_idct_sub_dual(s7[11], s7[20]);
|
||||
out[21] = highbd_idct_sub_dual(s7[10], s7[21]);
|
||||
out[22] = highbd_idct_sub_dual(s7[9], s7[22]);
|
||||
out[23] = highbd_idct_sub_dual(s7[8], s7[23]);
|
||||
out[24] = highbd_idct_sub_dual(s7[7], s7[24]);
|
||||
out[25] = highbd_idct_sub_dual(s7[6], s7[25]);
|
||||
out[26] = highbd_idct_sub_dual(s7[5], s7[26]);
|
||||
out[27] = highbd_idct_sub_dual(s7[4], s7[27]);
|
||||
out[28] = highbd_idct_sub_dual(s7[3], s6[28]);
|
||||
out[29] = highbd_idct_sub_dual(s7[2], s6[29]);
|
||||
out[30] = highbd_idct_sub_dual(s7[1], s6[30]);
|
||||
out[31] = highbd_idct_sub_dual(s7[0], s6[31]);
|
||||
|
||||
highbd_idct16x16_add_store(out, output, stride, bd);
|
||||
highbd_idct16x16_add_store(out + 16, output + 16 * stride, stride, bd);
|
||||
}
|
||||
|
||||
void vpx_highbd_idct32x32_135_add_neon(const tran_low_t *input, uint8_t *dest,
|
||||
int stride, int bd) {
|
||||
int i;
|
||||
|
||||
if (bd == 8) {
|
||||
int16_t temp[32 * 16];
|
||||
int16_t *t = temp;
|
||||
idct32_12_neon(input, temp);
|
||||
idct32_12_neon(input + 32 * 8, temp + 8);
|
||||
|
||||
for (i = 0; i < 32; i += 8) {
|
||||
idct32_16_neon(t, dest, stride, 1);
|
||||
t += (16 * 8);
|
||||
dest += 8;
|
||||
}
|
||||
} else {
|
||||
uint16_t *dst = CONVERT_TO_SHORTPTR(dest);
|
||||
int32_t temp[32 * 16];
|
||||
int32_t *t = temp;
|
||||
highbd_idct32_12_neon(input, temp);
|
||||
highbd_idct32_12_neon(input + 32 * 8, temp + 8);
|
||||
|
||||
for (i = 0; i < 32; i += 8) {
|
||||
highbd_idct32_16_neon(t, dst, stride, bd);
|
||||
t += (16 * 8);
|
||||
dst += 8;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -87,7 +87,7 @@ static INLINE void load_4x8_s16(const tran_low_t *input, int16x4_t *const in0,
|
||||
// 13 84 93 103 110 125
|
||||
// 14 98 106 115 127
|
||||
// 15 117 128
|
||||
static void idct32_12_neon(const tran_low_t *const input, int16_t *output) {
|
||||
void idct32_12_neon(const tran_low_t *const input, int16_t *output) {
|
||||
int16x4_t tmp[8];
|
||||
int16x8_t in[12], s1[32], s2[32], s3[32], s4[32], s5[32], s6[32], s7[32];
|
||||
|
||||
@ -371,10 +371,10 @@ static void idct32_12_neon(const tran_low_t *const input, int16_t *output) {
|
||||
vst1q_s16(output, vsubq_s16(s7[0], s6[31]));
|
||||
}
|
||||
|
||||
static void idct32_16_neon(const int16_t *const input, uint8_t *const output,
|
||||
const int stride) {
|
||||
void idct32_16_neon(const int16_t *const input, uint8_t *const output,
|
||||
const int stride, const int highbd_flag) {
|
||||
int16x8_t in[16], s1[32], s2[32], s3[32], s4[32], s5[32], s6[32], s7[32],
|
||||
out[8];
|
||||
out[32];
|
||||
|
||||
load_and_transpose_s16_8x8(input, 16, &in[0], &in[1], &in[2], &in[3], &in[4],
|
||||
&in[5], &in[6], &in[7]);
|
||||
@ -620,45 +620,44 @@ static void idct32_16_neon(const int16_t *const input, uint8_t *const output,
|
||||
out[5] = final_add(s7[5], s7[26]);
|
||||
out[6] = final_add(s7[6], s7[25]);
|
||||
out[7] = final_add(s7[7], s7[24]);
|
||||
out[8] = final_add(s7[8], s7[23]);
|
||||
out[9] = final_add(s7[9], s7[22]);
|
||||
out[10] = final_add(s7[10], s7[21]);
|
||||
out[11] = final_add(s7[11], s7[20]);
|
||||
out[12] = final_add(s7[12], s6[19]);
|
||||
out[13] = final_add(s7[13], s6[18]);
|
||||
out[14] = final_add(s7[14], s6[17]);
|
||||
out[15] = final_add(s7[15], s6[16]);
|
||||
out[16] = final_sub(s7[15], s6[16]);
|
||||
out[17] = final_sub(s7[14], s6[17]);
|
||||
out[18] = final_sub(s7[13], s6[18]);
|
||||
out[19] = final_sub(s7[12], s6[19]);
|
||||
out[20] = final_sub(s7[11], s7[20]);
|
||||
out[21] = final_sub(s7[10], s7[21]);
|
||||
out[22] = final_sub(s7[9], s7[22]);
|
||||
out[23] = final_sub(s7[8], s7[23]);
|
||||
out[24] = final_sub(s7[7], s7[24]);
|
||||
out[25] = final_sub(s7[6], s7[25]);
|
||||
out[26] = final_sub(s7[5], s7[26]);
|
||||
out[27] = final_sub(s7[4], s7[27]);
|
||||
out[28] = final_sub(s7[3], s6[28]);
|
||||
out[29] = final_sub(s7[2], s6[29]);
|
||||
out[30] = final_sub(s7[1], s6[30]);
|
||||
out[31] = final_sub(s7[0], s6[31]);
|
||||
|
||||
add_and_store_u8_s16(out[0], out[1], out[2], out[3], out[4], out[5], out[6],
|
||||
out[7], output, stride);
|
||||
|
||||
out[0] = final_add(s7[8], s7[23]);
|
||||
out[1] = final_add(s7[9], s7[22]);
|
||||
out[2] = final_add(s7[10], s7[21]);
|
||||
out[3] = final_add(s7[11], s7[20]);
|
||||
out[4] = final_add(s7[12], s6[19]);
|
||||
out[5] = final_add(s7[13], s6[18]);
|
||||
out[6] = final_add(s7[14], s6[17]);
|
||||
out[7] = final_add(s7[15], s6[16]);
|
||||
|
||||
add_and_store_u8_s16(out[0], out[1], out[2], out[3], out[4], out[5], out[6],
|
||||
out[7], output + (8 * stride), stride);
|
||||
|
||||
out[0] = final_sub(s7[15], s6[16]);
|
||||
out[1] = final_sub(s7[14], s6[17]);
|
||||
out[2] = final_sub(s7[13], s6[18]);
|
||||
out[3] = final_sub(s7[12], s6[19]);
|
||||
out[4] = final_sub(s7[11], s7[20]);
|
||||
out[5] = final_sub(s7[10], s7[21]);
|
||||
out[6] = final_sub(s7[9], s7[22]);
|
||||
out[7] = final_sub(s7[8], s7[23]);
|
||||
|
||||
add_and_store_u8_s16(out[0], out[1], out[2], out[3], out[4], out[5], out[6],
|
||||
out[7], output + (16 * stride), stride);
|
||||
|
||||
out[0] = final_sub(s7[7], s7[24]);
|
||||
out[1] = final_sub(s7[6], s7[25]);
|
||||
out[2] = final_sub(s7[5], s7[26]);
|
||||
out[3] = final_sub(s7[4], s7[27]);
|
||||
out[4] = final_sub(s7[3], s6[28]);
|
||||
out[5] = final_sub(s7[2], s6[29]);
|
||||
out[6] = final_sub(s7[1], s6[30]);
|
||||
out[7] = final_sub(s7[0], s6[31]);
|
||||
|
||||
add_and_store_u8_s16(out[0], out[1], out[2], out[3], out[4], out[5], out[6],
|
||||
out[7], output + (24 * stride), stride);
|
||||
if (highbd_flag) {
|
||||
uint16_t *const outputT = CONVERT_TO_SHORTPTR(output);
|
||||
highbd_add_and_store_bd8(out, outputT, stride);
|
||||
} else {
|
||||
add_and_store_u8_s16(out[0], out[1], out[2], out[3], out[4], out[5], out[6],
|
||||
out[7], output, stride);
|
||||
add_and_store_u8_s16(out[8], out[9], out[10], out[11], out[12], out[13],
|
||||
out[14], out[15], output + (8 * stride), stride);
|
||||
add_and_store_u8_s16(out[16], out[17], out[18], out[19], out[20], out[21],
|
||||
out[22], out[23], output + (16 * stride), stride);
|
||||
add_and_store_u8_s16(out[24], out[25], out[26], out[27], out[28], out[29],
|
||||
out[30], out[31], output + (24 * stride), stride);
|
||||
}
|
||||
}
|
||||
|
||||
void vpx_idct32x32_135_add_neon(const tran_low_t *input, uint8_t *dest,
|
||||
@ -671,7 +670,7 @@ void vpx_idct32x32_135_add_neon(const tran_low_t *input, uint8_t *dest,
|
||||
idct32_12_neon(input + 32 * 8, temp + 8);
|
||||
|
||||
for (i = 0; i < 32; i += 8) {
|
||||
idct32_16_neon(t, dest, stride);
|
||||
idct32_16_neon(t, dest, stride, 0);
|
||||
t += (16 * 8);
|
||||
dest += 8;
|
||||
}
|
||||
|
||||
@ -112,6 +112,24 @@ static INLINE int16x8_t final_sub(const int16x8_t a, const int16x8_t b) {
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
static INLINE int32x4x2_t highbd_idct_add_dual(const int32x4x2_t s0,
|
||||
const int32x4x2_t s1) {
|
||||
int32x4x2_t t;
|
||||
t.val[0] = vaddq_s32(s0.val[0], s1.val[0]);
|
||||
t.val[1] = vaddq_s32(s0.val[1], s1.val[1]);
|
||||
return t;
|
||||
}
|
||||
|
||||
static INLINE int32x4x2_t highbd_idct_sub_dual(const int32x4x2_t s0,
|
||||
const int32x4x2_t s1) {
|
||||
int32x4x2_t t;
|
||||
t.val[0] = vsubq_s32(s0.val[0], s1.val[0]);
|
||||
t.val[1] = vsubq_s32(s0.val[1], s1.val[1]);
|
||||
return t;
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// Multiply a by a_const. Saturate, shift and narrow by DCT_CONST_BITS.
|
||||
static INLINE int16x8_t multiply_shift_and_narrow_s16(const int16x8_t a,
|
||||
const int16_t a_const) {
|
||||
@ -169,6 +187,87 @@ static INLINE int16x8_t multiply_accumulate_shift_and_narrow_s16(
|
||||
vrshrn_n_s32(temp_high, DCT_CONST_BITS));
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// Note: The following 4 functions could use 32-bit operations for bit-depth 10.
|
||||
// However, although it's 20% faster with gcc, it's 20% slower with clang.
|
||||
// Use 64-bit operations for now.
|
||||
|
||||
// Multiply a by a_const. Saturate, shift and narrow by DCT_CONST_BITS.
|
||||
static INLINE int32x4x2_t
|
||||
multiply_shift_and_narrow_s32_dual(const int32x4x2_t a, const int32_t a_const) {
|
||||
int64x2_t b[4];
|
||||
int32x4x2_t c;
|
||||
b[0] = vmull_n_s32(vget_low_s32(a.val[0]), a_const);
|
||||
b[1] = vmull_n_s32(vget_high_s32(a.val[0]), a_const);
|
||||
b[2] = vmull_n_s32(vget_low_s32(a.val[1]), a_const);
|
||||
b[3] = vmull_n_s32(vget_high_s32(a.val[1]), a_const);
|
||||
c.val[0] = vcombine_s32(vrshrn_n_s64(b[0], DCT_CONST_BITS),
|
||||
vrshrn_n_s64(b[1], DCT_CONST_BITS));
|
||||
c.val[1] = vcombine_s32(vrshrn_n_s64(b[2], DCT_CONST_BITS),
|
||||
vrshrn_n_s64(b[3], DCT_CONST_BITS));
|
||||
return c;
|
||||
}
|
||||
|
||||
// Add a and b, then multiply by ab_const. Shift and narrow by DCT_CONST_BITS.
|
||||
static INLINE int32x4x2_t add_multiply_shift_and_narrow_s32_dual(
|
||||
const int32x4x2_t a, const int32x4x2_t b, const int32_t ab_const) {
|
||||
const int32x4_t temp_low = vaddq_s32(a.val[0], b.val[0]);
|
||||
const int32x4_t temp_high = vaddq_s32(a.val[1], b.val[1]);
|
||||
int64x2_t c[4];
|
||||
int32x4x2_t d;
|
||||
c[0] = vmull_n_s32(vget_low_s32(temp_low), ab_const);
|
||||
c[1] = vmull_n_s32(vget_high_s32(temp_low), ab_const);
|
||||
c[2] = vmull_n_s32(vget_low_s32(temp_high), ab_const);
|
||||
c[3] = vmull_n_s32(vget_high_s32(temp_high), ab_const);
|
||||
d.val[0] = vcombine_s32(vrshrn_n_s64(c[0], DCT_CONST_BITS),
|
||||
vrshrn_n_s64(c[1], DCT_CONST_BITS));
|
||||
d.val[1] = vcombine_s32(vrshrn_n_s64(c[2], DCT_CONST_BITS),
|
||||
vrshrn_n_s64(c[3], DCT_CONST_BITS));
|
||||
return d;
|
||||
}
|
||||
|
||||
// Subtract b from a, then multiply by ab_const. Shift and narrow by
|
||||
// DCT_CONST_BITS.
|
||||
static INLINE int32x4x2_t sub_multiply_shift_and_narrow_s32_dual(
|
||||
const int32x4x2_t a, const int32x4x2_t b, const int32_t ab_const) {
|
||||
const int32x4_t temp_low = vsubq_s32(a.val[0], b.val[0]);
|
||||
const int32x4_t temp_high = vsubq_s32(a.val[1], b.val[1]);
|
||||
int64x2_t c[4];
|
||||
int32x4x2_t d;
|
||||
c[0] = vmull_n_s32(vget_low_s32(temp_low), ab_const);
|
||||
c[1] = vmull_n_s32(vget_high_s32(temp_low), ab_const);
|
||||
c[2] = vmull_n_s32(vget_low_s32(temp_high), ab_const);
|
||||
c[3] = vmull_n_s32(vget_high_s32(temp_high), ab_const);
|
||||
d.val[0] = vcombine_s32(vrshrn_n_s64(c[0], DCT_CONST_BITS),
|
||||
vrshrn_n_s64(c[1], DCT_CONST_BITS));
|
||||
d.val[1] = vcombine_s32(vrshrn_n_s64(c[2], DCT_CONST_BITS),
|
||||
vrshrn_n_s64(c[3], DCT_CONST_BITS));
|
||||
return d;
|
||||
}
|
||||
|
||||
// Multiply a by a_const and b by b_const, then accumulate. Shift and narrow by
|
||||
// DCT_CONST_BITS.
|
||||
static INLINE int32x4x2_t multiply_accumulate_shift_and_narrow_s32_dual(
|
||||
const int32x4x2_t a, const int32_t a_const, const int32x4x2_t b,
|
||||
const int32_t b_const) {
|
||||
int64x2_t c[4];
|
||||
int32x4x2_t d;
|
||||
c[0] = vmull_n_s32(vget_low_s32(a.val[0]), a_const);
|
||||
c[1] = vmull_n_s32(vget_high_s32(a.val[0]), a_const);
|
||||
c[2] = vmull_n_s32(vget_low_s32(a.val[1]), a_const);
|
||||
c[3] = vmull_n_s32(vget_high_s32(a.val[1]), a_const);
|
||||
c[0] = vmlal_n_s32(c[0], vget_low_s32(b.val[0]), b_const);
|
||||
c[1] = vmlal_n_s32(c[1], vget_high_s32(b.val[0]), b_const);
|
||||
c[2] = vmlal_n_s32(c[2], vget_low_s32(b.val[1]), b_const);
|
||||
c[3] = vmlal_n_s32(c[3], vget_high_s32(b.val[1]), b_const);
|
||||
d.val[0] = vcombine_s32(vrshrn_n_s64(c[0], DCT_CONST_BITS),
|
||||
vrshrn_n_s64(c[1], DCT_CONST_BITS));
|
||||
d.val[1] = vcombine_s32(vrshrn_n_s64(c[2], DCT_CONST_BITS),
|
||||
vrshrn_n_s64(c[3], DCT_CONST_BITS));
|
||||
return d;
|
||||
}
|
||||
|
||||
// Shift the output down by 6 and add it to the destination buffer.
|
||||
static INLINE void add_and_store_u8_s16(const int16x8_t a0, const int16x8_t a1,
|
||||
const int16x8_t a2, const int16x8_t a3,
|
||||
@ -762,6 +861,108 @@ static INLINE void highbd_idct16x16_add8x1(int16x8_t res, const int16x8_t max,
|
||||
*dest += stride;
|
||||
}
|
||||
|
||||
static INLINE void highbd_idct16x16_add8x1_bd8(int16x8_t res, uint16_t **dest,
|
||||
const int stride) {
|
||||
uint16x8_t d = vld1q_u16(*dest);
|
||||
|
||||
res = vrsraq_n_s16(vreinterpretq_s16_u16(d), res, 6);
|
||||
d = vmovl_u8(vqmovun_s16(res));
|
||||
vst1q_u16(*dest, d);
|
||||
*dest += stride;
|
||||
}
|
||||
|
||||
static INLINE void highbd_add_and_store_bd8(const int16x8_t *const a,
|
||||
uint16_t *out, const int b_stride) {
|
||||
highbd_idct16x16_add8x1_bd8(a[0], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[1], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[2], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[3], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[4], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[5], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[6], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[7], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[8], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[9], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[10], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[11], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[12], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[13], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[14], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[15], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[16], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[17], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[18], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[19], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[20], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[21], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[22], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[23], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[24], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[25], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[26], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[27], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[28], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[29], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[30], &out, b_stride);
|
||||
highbd_idct16x16_add8x1_bd8(a[31], &out, b_stride);
|
||||
}
|
||||
|
||||
static INLINE void highbd_idct16x16_add_store(const int32x4x2_t *const out,
|
||||
uint16_t *dest, const int stride,
|
||||
const int bd) {
|
||||
// Add the result to dest
|
||||
const int16x8_t max = vdupq_n_s16((1 << bd) - 1);
|
||||
int16x8_t o[16];
|
||||
o[0] = vcombine_s16(vrshrn_n_s32(out[0].val[0], 6),
|
||||
vrshrn_n_s32(out[0].val[1], 6));
|
||||
o[1] = vcombine_s16(vrshrn_n_s32(out[1].val[0], 6),
|
||||
vrshrn_n_s32(out[1].val[1], 6));
|
||||
o[2] = vcombine_s16(vrshrn_n_s32(out[2].val[0], 6),
|
||||
vrshrn_n_s32(out[2].val[1], 6));
|
||||
o[3] = vcombine_s16(vrshrn_n_s32(out[3].val[0], 6),
|
||||
vrshrn_n_s32(out[3].val[1], 6));
|
||||
o[4] = vcombine_s16(vrshrn_n_s32(out[4].val[0], 6),
|
||||
vrshrn_n_s32(out[4].val[1], 6));
|
||||
o[5] = vcombine_s16(vrshrn_n_s32(out[5].val[0], 6),
|
||||
vrshrn_n_s32(out[5].val[1], 6));
|
||||
o[6] = vcombine_s16(vrshrn_n_s32(out[6].val[0], 6),
|
||||
vrshrn_n_s32(out[6].val[1], 6));
|
||||
o[7] = vcombine_s16(vrshrn_n_s32(out[7].val[0], 6),
|
||||
vrshrn_n_s32(out[7].val[1], 6));
|
||||
o[8] = vcombine_s16(vrshrn_n_s32(out[8].val[0], 6),
|
||||
vrshrn_n_s32(out[8].val[1], 6));
|
||||
o[9] = vcombine_s16(vrshrn_n_s32(out[9].val[0], 6),
|
||||
vrshrn_n_s32(out[9].val[1], 6));
|
||||
o[10] = vcombine_s16(vrshrn_n_s32(out[10].val[0], 6),
|
||||
vrshrn_n_s32(out[10].val[1], 6));
|
||||
o[11] = vcombine_s16(vrshrn_n_s32(out[11].val[0], 6),
|
||||
vrshrn_n_s32(out[11].val[1], 6));
|
||||
o[12] = vcombine_s16(vrshrn_n_s32(out[12].val[0], 6),
|
||||
vrshrn_n_s32(out[12].val[1], 6));
|
||||
o[13] = vcombine_s16(vrshrn_n_s32(out[13].val[0], 6),
|
||||
vrshrn_n_s32(out[13].val[1], 6));
|
||||
o[14] = vcombine_s16(vrshrn_n_s32(out[14].val[0], 6),
|
||||
vrshrn_n_s32(out[14].val[1], 6));
|
||||
o[15] = vcombine_s16(vrshrn_n_s32(out[15].val[0], 6),
|
||||
vrshrn_n_s32(out[15].val[1], 6));
|
||||
highbd_idct16x16_add8x1(o[0], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[1], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[2], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[3], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[4], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[5], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[6], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[7], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[8], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[9], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[10], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[11], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[12], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[13], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[14], max, &dest, stride);
|
||||
highbd_idct16x16_add8x1(o[15], max, &dest, stride);
|
||||
}
|
||||
|
||||
void idct16x16_256_add_half1d(const void *const input, int16_t *output,
|
||||
void *const dest, const int stride,
|
||||
const int highbd_flag);
|
||||
@ -776,4 +977,8 @@ void idct16x16_10_add_half1d_pass2(const int16_t *input, int16_t *const output,
|
||||
void *const dest, const int stride,
|
||||
const int highbd_flag);
|
||||
|
||||
void idct32_12_neon(const tran_low_t *const input, int16_t *output);
|
||||
void idct32_16_neon(const int16_t *const input, uint8_t *const output,
|
||||
const int stride, const int highbd_flag);
|
||||
|
||||
#endif // VPX_DSP_ARM_IDCT_NEON_H_
|
||||
|
||||
@ -1281,4 +1281,36 @@ static INLINE void load_and_transpose_s16_8x8(const int16_t *a,
|
||||
|
||||
transpose_s16_8x8(a0, a1, a2, a3, a4, a5, a6, a7);
|
||||
}
|
||||
|
||||
static INLINE void load_and_transpose_s32_8x8(
|
||||
const int32_t *a, const int a_stride, int32x4x2_t *const a0,
|
||||
int32x4x2_t *const a1, int32x4x2_t *const a2, int32x4x2_t *const a3,
|
||||
int32x4x2_t *const a4, int32x4x2_t *const a5, int32x4x2_t *const a6,
|
||||
int32x4x2_t *const a7) {
|
||||
a0->val[0] = vld1q_s32(a);
|
||||
a0->val[1] = vld1q_s32(a + 4);
|
||||
a += a_stride;
|
||||
a1->val[0] = vld1q_s32(a);
|
||||
a1->val[1] = vld1q_s32(a + 4);
|
||||
a += a_stride;
|
||||
a2->val[0] = vld1q_s32(a);
|
||||
a2->val[1] = vld1q_s32(a + 4);
|
||||
a += a_stride;
|
||||
a3->val[0] = vld1q_s32(a);
|
||||
a3->val[1] = vld1q_s32(a + 4);
|
||||
a += a_stride;
|
||||
a4->val[0] = vld1q_s32(a);
|
||||
a4->val[1] = vld1q_s32(a + 4);
|
||||
a += a_stride;
|
||||
a5->val[0] = vld1q_s32(a);
|
||||
a5->val[1] = vld1q_s32(a + 4);
|
||||
a += a_stride;
|
||||
a6->val[0] = vld1q_s32(a);
|
||||
a6->val[1] = vld1q_s32(a + 4);
|
||||
a += a_stride;
|
||||
a7->val[0] = vld1q_s32(a);
|
||||
a7->val[1] = vld1q_s32(a + 4);
|
||||
|
||||
transpose_s32_8x8(a0, a1, a2, a3, a4, a5, a6, a7);
|
||||
}
|
||||
#endif // VPX_DSP_ARM_TRANSPOSE_NEON_H_
|
||||
|
||||
@ -224,6 +224,7 @@ DSP_SRCS-$(HAVE_NEON) += arm/highbd_idct4x4_add_neon.c
|
||||
DSP_SRCS-$(HAVE_NEON) += arm/highbd_idct8x8_add_neon.c
|
||||
DSP_SRCS-$(HAVE_NEON) += arm/highbd_idct16x16_add_neon.c
|
||||
DSP_SRCS-$(HAVE_NEON) += arm/highbd_idct32x32_add_neon.c
|
||||
DSP_SRCS-$(HAVE_NEON) += arm/highbd_idct32x32_135_add_neon.c
|
||||
endif # !CONFIG_VP9_HIGHBITDEPTH
|
||||
|
||||
ifeq ($(HAVE_NEON_ASM),yes)
|
||||
|
||||
@ -628,8 +628,6 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
|
||||
|
||||
add_proto qw/void vpx_highbd_idct32x32_1024_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
|
||||
|
||||
add_proto qw/void vpx_highbd_idct32x32_135_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
|
||||
|
||||
add_proto qw/void vpx_highbd_idct32x32_34_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
|
||||
|
||||
add_proto qw/void vpx_highbd_idct32x32_1_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
|
||||
@ -678,6 +676,8 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
|
||||
add_proto qw/void vpx_highbd_idct16x16_38_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
|
||||
|
||||
add_proto qw/void vpx_highbd_idct16x16_10_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
|
||||
|
||||
add_proto qw/void vpx_highbd_idct32x32_135_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
|
||||
} else {
|
||||
add_proto qw/void vpx_idct4x4_16_add/, "const tran_low_t *input, uint8_t *dest, int stride";
|
||||
specialize qw/vpx_idct4x4_16_add neon sse2/;
|
||||
@ -739,6 +739,9 @@ if (vpx_config("CONFIG_VP9_HIGHBITDEPTH") eq "yes") {
|
||||
|
||||
add_proto qw/void vpx_highbd_idct16x16_10_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
|
||||
specialize qw/vpx_highbd_idct16x16_10_add neon sse2/;
|
||||
|
||||
add_proto qw/void vpx_highbd_idct32x32_135_add/, "const tran_low_t *input, uint8_t *dest, int stride, int bd";
|
||||
specialize qw/vpx_highbd_idct32x32_135_add neon/;
|
||||
} # CONFIG_EMULATE_HARDWARE
|
||||
} else {
|
||||
# Force C versions if CONFIG_EMULATE_HARDWARE is 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user