Enable SSSE3 implementation of 8x8 forward 2D-DCT
Assembly implementation of ssse3 8x8 forward 2D-DCT. The current version is turned on only for x86_64. The average unit runtime goes from 157 cycles down to 136 cycles, i.e., about 12.8% faster. This translates into about 1.5% speed-up for pedestrian_area 1080p at speed 2. Change-Id: I0f12435857e9425ed7ce12541344dfa16837f4f4
This commit is contained in:
Jingning Han
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e38ca5422c
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1eaa3a76dc
@ -743,7 +743,7 @@ add_proto qw/void vp9_fdct4x4/, "const int16_t *input, int16_t *output, int stri
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specialize qw/vp9_fdct4x4 sse2 avx2/;
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specialize qw/vp9_fdct4x4 sse2 avx2/;
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add_proto qw/void vp9_fdct8x8/, "const int16_t *input, int16_t *output, int stride";
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add_proto qw/void vp9_fdct8x8/, "const int16_t *input, int16_t *output, int stride";
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specialize qw/vp9_fdct8x8 sse2 avx2/;
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specialize qw/vp9_fdct8x8 sse2 avx2/, "$ssse3_x86_64";
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add_proto qw/void vp9_fdct16x16/, "const int16_t *input, int16_t *output, int stride";
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add_proto qw/void vp9_fdct16x16/, "const int16_t *input, int16_t *output, int stride";
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specialize qw/vp9_fdct16x16 sse2 avx2/;
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specialize qw/vp9_fdct16x16 sse2 avx2/;
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174
vp9/encoder/x86/vp9_dct_ssse3.asm
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174
vp9/encoder/x86/vp9_dct_ssse3.asm
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@ -0,0 +1,174 @@
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;
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; Copyright (c) 2014 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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%include "third_party/x86inc/x86inc.asm"
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; This file provides SSSE3 version of the forward transformation. Part
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; of the macro definitions are originally derived from ffmpeg project.
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; The current version applies to x86 64-bit only.
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SECTION_RODATA
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pw_11585x2: times 8 dw 23170
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pd_8192: times 4 dd 8192
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%macro TRANSFORM_COEFFS 2
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pw_%1_%2: dw %1, %2, %1, %2, %1, %2, %1, %2
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pw_%2_m%1: dw %2, -%1, %2, -%1, %2, -%1, %2, -%1
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%endmacro
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TRANSFORM_COEFFS 15137, 6270
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TRANSFORM_COEFFS 16069, 3196
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TRANSFORM_COEFFS 9102, 13623
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SECTION .text
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%if ARCH_X86_64
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%macro SUM_SUB 3
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psubw m%3, m%1, m%2
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paddw m%1, m%2
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SWAP %2, %3
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%endmacro
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; butterfly operation
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%macro MUL_ADD_2X 6 ; dst1, dst2, src, round, coefs1, coefs2
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pmaddwd m%1, m%3, %5
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pmaddwd m%2, m%3, %6
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paddd m%1, %4
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paddd m%2, %4
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psrad m%1, 14
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psrad m%2, 14
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%endmacro
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%macro BUTTERFLY_4X 7 ; dst1, dst2, coef1, coef2, round, tmp1, tmp2
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punpckhwd m%6, m%2, m%1
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MUL_ADD_2X %7, %6, %6, %5, [pw_%4_%3], [pw_%3_m%4]
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punpcklwd m%2, m%1
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MUL_ADD_2X %1, %2, %2, %5, [pw_%4_%3], [pw_%3_m%4]
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packssdw m%1, m%7
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packssdw m%2, m%6
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%endmacro
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; matrix transpose
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%macro INTERLEAVE_2X 4
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punpckh%1 m%4, m%2, m%3
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punpckl%1 m%2, m%3
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SWAP %3, %4
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%endmacro
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%macro TRANSPOSE8X8 9
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INTERLEAVE_2X wd, %1, %2, %9
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INTERLEAVE_2X wd, %3, %4, %9
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INTERLEAVE_2X wd, %5, %6, %9
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INTERLEAVE_2X wd, %7, %8, %9
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INTERLEAVE_2X dq, %1, %3, %9
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INTERLEAVE_2X dq, %2, %4, %9
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INTERLEAVE_2X dq, %5, %7, %9
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INTERLEAVE_2X dq, %6, %8, %9
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INTERLEAVE_2X qdq, %1, %5, %9
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INTERLEAVE_2X qdq, %3, %7, %9
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INTERLEAVE_2X qdq, %2, %6, %9
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INTERLEAVE_2X qdq, %4, %8, %9
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SWAP %2, %5
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SWAP %4, %7
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%endmacro
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; 1D forward 8x8 DCT transform
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%macro FDCT8_1D 0
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SUM_SUB 0, 7, 9
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SUM_SUB 1, 6, 9
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SUM_SUB 2, 5, 9
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SUM_SUB 3, 4, 9
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SUM_SUB 0, 3, 9
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SUM_SUB 1, 2, 9
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SUM_SUB 6, 5, 9
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SUM_SUB 0, 1, 9
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BUTTERFLY_4X 2, 3, 6270, 15137, m8, 9, 10
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pmulhrsw m6, m12
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pmulhrsw m5, m12
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pmulhrsw m0, m12
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pmulhrsw m1, m12
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SUM_SUB 4, 5, 9
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SUM_SUB 7, 6, 9
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BUTTERFLY_4X 4, 7, 3196, 16069, m8, 9, 10
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BUTTERFLY_4X 5, 6, 13623, 9102, m8, 9, 10
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SWAP 1, 4
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SWAP 3, 6
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%endmacro
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%macro DIVIDE_ROUND_2X 4 ; dst1, dst2, tmp1, tmp2
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psraw m%3, m%1, 15
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psraw m%4, m%2, 15
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psubw m%1, m%3
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psubw m%2, m%4
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psraw m%1, 1
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psraw m%2, 1
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%endmacro
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INIT_XMM ssse3
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cglobal fdct8x8, 3, 5, 13, input, output, stride
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mova m8, [pd_8192]
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mova m12, [pw_11585x2]
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pxor m11, m11
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lea r3, [2 * strideq]
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lea r4, [4 * strideq]
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mova m0, [inputq]
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mova m1, [inputq + r3]
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lea inputq, [inputq + r4]
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mova m2, [inputq]
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mova m3, [inputq + r3]
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lea inputq, [inputq + r4]
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mova m4, [inputq]
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mova m5, [inputq + r3]
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lea inputq, [inputq + r4]
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mova m6, [inputq]
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mova m7, [inputq + r3]
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; left shift by 2 to increase forward transformation precision
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psllw m0, 2
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psllw m1, 2
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psllw m2, 2
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psllw m3, 2
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psllw m4, 2
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psllw m5, 2
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psllw m6, 2
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psllw m7, 2
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; column transform
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FDCT8_1D
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TRANSPOSE8X8 0, 1, 2, 3, 4, 5, 6, 7, 9
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FDCT8_1D
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TRANSPOSE8X8 0, 1, 2, 3, 4, 5, 6, 7, 9
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DIVIDE_ROUND_2X 0, 1, 9, 10
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DIVIDE_ROUND_2X 2, 3, 9, 10
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DIVIDE_ROUND_2X 4, 5, 9, 10
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DIVIDE_ROUND_2X 6, 7, 9, 10
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mova [outputq + 0], m0
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mova [outputq + 16], m1
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mova [outputq + 32], m2
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mova [outputq + 48], m3
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mova [outputq + 64], m4
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mova [outputq + 80], m5
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mova [outputq + 96], m6
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mova [outputq + 112], m7
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RET
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%endif
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@ -112,6 +112,7 @@ endif
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ifeq ($(ARCH_X86_64),yes)
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ifeq ($(ARCH_X86_64),yes)
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VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_quantize_ssse3.asm
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VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_quantize_ssse3.asm
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VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_dct_ssse3.asm
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endif
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endif
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VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_sad_ssse3.asm
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VP9_CX_SRCS-$(HAVE_SSSE3) += encoder/x86/vp9_sad_ssse3.asm
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VP9_CX_SRCS-$(HAVE_SSE4_1) += encoder/x86/vp9_sad_sse4.asm
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VP9_CX_SRCS-$(HAVE_SSE4_1) += encoder/x86/vp9_sad_sse4.asm
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