mips msa vp9 block error optimization
average improvement ~3x-4x Change-Id: If0fdcc34b17437a7e3e7fb4caaf1067bc175f291
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@@ -440,6 +440,17 @@
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}
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#define ST_SH8(...) ST_H8(v8i16, __VA_ARGS__)
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/* Description : Store vectors of word elements with stride
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Arguments : Inputs - in0, in1, stride
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- pdst (destination pointer to store to)
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Details : Store 4 word elements from 'in0' to (pdst)
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Store 4 word elements from 'in1' to (pdst + stride)
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*/
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#define ST_SW2(in0, in1, pdst, stride) { \
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ST_SW(in0, (pdst)); \
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ST_SW(in1, (pdst) + stride); \
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}
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/* Description : Store as 2x4 byte block to destination memory from input vector
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Arguments : Inputs - in, stidx, pdst, stride
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Return Type - unsigned byte
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@@ -781,6 +792,39 @@
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}
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#define DPADD_SB4_SH(...) DPADD_SB4(v8i16, __VA_ARGS__)
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/* Description : Dot product & addition of halfword vector elements
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Arguments : Inputs - mult0, mult1
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cnst0, cnst1
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Signed halfword elements from 'mult0' are multiplied with
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signed halfword elements from 'cnst0' producing a result
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twice the size of input i.e. signed word.
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The multiplication result of adjacent odd-even elements
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are added to the 'out0' vector
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*/
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#define DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) { \
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out0 = (RTYPE)__msa_dpadd_s_w((v4i32)out0, (v8i16)mult0, (v8i16)cnst0); \
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out1 = (RTYPE)__msa_dpadd_s_w((v4i32)out1, (v8i16)mult1, (v8i16)cnst1); \
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}
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#define DPADD_SH2_SW(...) DPADD_SH2(v4i32, __VA_ARGS__)
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/* Description : Dot product & addition of double word vector elements
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Arguments : Inputs - mult0, mult1
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Each signed word element from 'mult0' is multiplied with itself
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producing an intermediate result twice the size of input
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i.e. signed double word
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The multiplication result of adjacent odd-even elements
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are added to the 'out0' vector
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*/
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#define DPADD_SD2(RTYPE, mult0, mult1, out0, out1) { \
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out0 = (RTYPE)__msa_dpadd_s_d((v2i64)out0, (v4i32)mult0, (v4i32)mult0); \
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out1 = (RTYPE)__msa_dpadd_s_d((v2i64)out1, (v4i32)mult1, (v4i32)mult1); \
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}
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#define DPADD_SD2_SD(...) DPADD_SD2(v2i64, __VA_ARGS__)
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/* Description : Minimum values between unsigned elements of
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either vector are copied to the output vector
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Arguments : Inputs - in0, in1, min_vec
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@@ -862,6 +906,34 @@
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}
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#define HADD_UB4_UH(...) HADD_UB4(v8u16, __VA_ARGS__)
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/* Description : Horizontal subtraction of unsigned byte vector elements
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Arguments : Inputs - in0, in1
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Each unsigned odd byte element from 'in0' is subtracted from
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even unsigned byte element from 'in0' (pairwise) and the
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halfword result is written to 'out0'
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*/
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#define HSUB_UB2(RTYPE, in0, in1, out0, out1) { \
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out0 = (RTYPE)__msa_hsub_u_h((v16u8)in0, (v16u8)in0); \
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out1 = (RTYPE)__msa_hsub_u_h((v16u8)in1, (v16u8)in1); \
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}
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#define HSUB_UB2_SH(...) HSUB_UB2(v8i16, __VA_ARGS__)
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/* Description : Horizontal subtraction of signed halfword vector elements
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Arguments : Inputs - in0, in1
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Outputs - out0, out1
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Return Type - as per RTYPE
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Details : Each signed odd halfword element from 'in0' is subtracted from
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even signed halfword element from 'in0' (pairwise) and the
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word result is written to 'out0'
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*/
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#define HSUB_UH2(RTYPE, in0, in1, out0, out1) { \
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out0 = (RTYPE)__msa_hsub_s_w((v8i16)in0, (v8i16)in0); \
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out1 = (RTYPE)__msa_hsub_s_w((v8i16)in1, (v8i16)in1); \
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}
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#define HSUB_UH2_SW(...) HSUB_UH2(v4i32, __VA_ARGS__)
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/* Description : Insert specified word elements from input vectors to 1
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destination vector
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Arguments : Inputs - in0, in1, in2, in3 (4 input vectors)
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