2010-05-18 17:58:33 +02:00
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;
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2010-09-09 14:16:39 +02:00
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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2010-05-18 17:58:33 +02:00
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;
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2010-06-18 18:39:21 +02:00
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; Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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; in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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; be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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;
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EXPORT |vp8_short_fdct4x4_neon|
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EXPORT |vp8_short_fdct8x4_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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; r0 short *input
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; r1 short *output
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; r2 int pitch
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; Input has a pitch, output is contiguous
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|vp8_short_fdct4x4_neon| PROC
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ldr r12, _dct_matrix_
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vld1.16 d0, [r0], r2
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vld1.16 d1, [r0], r2
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vld1.16 d2, [r0], r2
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vld1.16 d3, [r0]
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vld1.16 {q2, q3}, [r12]
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;first stage
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vmull.s16 q11, d4, d0[0] ;i=0
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vmull.s16 q12, d4, d1[0] ;i=1
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vmull.s16 q13, d4, d2[0] ;i=2
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vmull.s16 q14, d4, d3[0] ;i=3
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vmlal.s16 q11, d5, d0[1]
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vmlal.s16 q12, d5, d1[1]
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vmlal.s16 q13, d5, d2[1]
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vmlal.s16 q14, d5, d3[1]
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vmlal.s16 q11, d6, d0[2]
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vmlal.s16 q12, d6, d1[2]
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vmlal.s16 q13, d6, d2[2]
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vmlal.s16 q14, d6, d3[2]
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vmlal.s16 q11, d7, d0[3] ;sumtemp for i=0
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vmlal.s16 q12, d7, d1[3] ;sumtemp for i=1
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vmlal.s16 q13, d7, d2[3] ;sumtemp for i=2
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vmlal.s16 q14, d7, d3[3] ;sumtemp for i=3
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; rounding
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vrshrn.i32 d22, q11, #14
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vrshrn.i32 d24, q12, #14
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vrshrn.i32 d26, q13, #14
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vrshrn.i32 d28, q14, #14
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;second stage
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vmull.s16 q4, d22, d4[0] ;i=0
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vmull.s16 q5, d22, d4[1] ;i=1
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vmull.s16 q6, d22, d4[2] ;i=2
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vmull.s16 q7, d22, d4[3] ;i=3
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vmlal.s16 q4, d24, d5[0]
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vmlal.s16 q5, d24, d5[1]
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vmlal.s16 q6, d24, d5[2]
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vmlal.s16 q7, d24, d5[3]
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vmlal.s16 q4, d26, d6[0]
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vmlal.s16 q5, d26, d6[1]
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vmlal.s16 q6, d26, d6[2]
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vmlal.s16 q7, d26, d6[3]
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vmlal.s16 q4, d28, d7[0] ;sumtemp for i=0
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vmlal.s16 q5, d28, d7[1] ;sumtemp for i=1
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vmlal.s16 q6, d28, d7[2] ;sumtemp for i=2
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vmlal.s16 q7, d28, d7[3] ;sumtemp for i=3
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vrshr.s32 q0, q4, #16
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vrshr.s32 q1, q5, #16
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vrshr.s32 q2, q6, #16
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vrshr.s32 q3, q7, #16
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vmovn.i32 d0, q0
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vmovn.i32 d1, q1
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vmovn.i32 d2, q2
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vmovn.i32 d3, q3
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vst1.16 {q0, q1}, [r1]
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bx lr
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ENDP
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; r0 short *input
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; r1 short *output
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; r2 int pitch
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|vp8_short_fdct8x4_neon| PROC
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; Store link register and input before calling
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; first 4x4 fdct. Do not need to worry about
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; output or pitch because those pointers are not
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; touched in the 4x4 fdct function
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stmdb sp!, {r0, lr}
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bl vp8_short_fdct4x4_neon
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ldmia sp!, {r0, lr}
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; Move to the next block of data.
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add r0, r0, #8
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add r1, r1, #32
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; Second time through do not store off the
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; link register, just return from the 4x4 fdtc
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b vp8_short_fdct4x4_neon
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; Should never get to this.
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bx lr
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ENDP
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;-----------------
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AREA dct4x4_dat, DATA, READONLY
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;Data section with name data_area is specified. DCD reserves space in memory for 48 data.
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;One word each is reserved. Label filter_coeff can be used to access the data.
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;Data address: filter_coeff, filter_coeff+4, filter_coeff+8 ...
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_dct_matrix_
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DCD dct_matrix
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dct_matrix
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; DCW 23170, 30274, 23170, 12540
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; DCW 23170, 12540, -23170,-30274
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; DCW 23170, -12540, -23170, 30274
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; DCW 23170, -30274, 23170,-12540
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; 23170 = 0x5a82
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; -23170 = 0xa57e
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; 30274 = 0x7642
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; -30274 = 0x89be
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; 12540 = 0x30fc
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; -12540 = 0xcf04
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DCD 0x76425a82, 0x30fc5a82
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DCD 0x30fc5a82, 0x89bea57e
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DCD 0xcf045a82, 0x7642a57e
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DCD 0x89be5a82, 0xcf045a82
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END
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