2010-05-18 17:58:33 +02:00
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;
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2010-09-09 14:16:39 +02:00
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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2010-05-18 17:58:33 +02:00
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;
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2010-06-18 18:39:21 +02:00
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; Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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; in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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; be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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;
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EXPORT |vp8_short_idct4x4llm_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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;*************************************************************
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;void vp8_short_idct4x4llm_c(short *input, short *output, int pitch)
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;r0 short * input
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;r1 short * output
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;r2 int pitch
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;*************************************************************
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;static const int cospi8sqrt2minus1=20091;
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;static const int sinpi8sqrt2 =35468;
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;static const int rounding = 0;
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;Optimization note: The resulted data from dequantization are signed 13-bit data that is
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;in the range of [-4096, 4095]. This allows to use "vqdmulh"(neon) instruction since
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;it won't go out of range (13+16+1=30bits<32bits). This instruction gives the high half
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;result of the multiplication that is needed in IDCT.
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|vp8_short_idct4x4llm_neon| PROC
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2011-06-17 02:33:52 +02:00
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adr r12, idct_coeff
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2010-05-18 17:58:33 +02:00
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vld1.16 {q1, q2}, [r0]
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vld1.16 {d0}, [r12]
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vswp d3, d4 ;q2(vp[4] vp[12])
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vqdmulh.s16 q3, q2, d0[2]
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vqdmulh.s16 q4, q2, d0[0]
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vqadd.s16 d12, d2, d3 ;a1
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vqsub.s16 d13, d2, d3 ;b1
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vshr.s16 q3, q3, #1
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vshr.s16 q4, q4, #1
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vqadd.s16 q3, q3, q2 ;modify since sinpi8sqrt2 > 65536/2 (negtive number)
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vqadd.s16 q4, q4, q2
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;d6 - c1:temp1
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;d7 - d1:temp2
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;d8 - d1:temp1
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;d9 - c1:temp2
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vqsub.s16 d10, d6, d9 ;c1
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vqadd.s16 d11, d7, d8 ;d1
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vqadd.s16 d2, d12, d11
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vqadd.s16 d3, d13, d10
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vqsub.s16 d4, d13, d10
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vqsub.s16 d5, d12, d11
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vtrn.32 d2, d4
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vtrn.32 d3, d5
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vtrn.16 d2, d3
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vtrn.16 d4, d5
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vswp d3, d4
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vqdmulh.s16 q3, q2, d0[2]
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vqdmulh.s16 q4, q2, d0[0]
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vqadd.s16 d12, d2, d3 ;a1
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vqsub.s16 d13, d2, d3 ;b1
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vshr.s16 q3, q3, #1
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vshr.s16 q4, q4, #1
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vqadd.s16 q3, q3, q2 ;modify since sinpi8sqrt2 > 65536/2 (negtive number)
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vqadd.s16 q4, q4, q2
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vqsub.s16 d10, d6, d9 ;c1
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vqadd.s16 d11, d7, d8 ;d1
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vqadd.s16 d2, d12, d11
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vqadd.s16 d3, d13, d10
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vqsub.s16 d4, d13, d10
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vqsub.s16 d5, d12, d11
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vrshr.s16 d2, d2, #3
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vrshr.s16 d3, d3, #3
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vrshr.s16 d4, d4, #3
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vrshr.s16 d5, d5, #3
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add r3, r1, r2
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add r12, r3, r2
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add r0, r12, r2
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vtrn.32 d2, d4
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vtrn.32 d3, d5
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vtrn.16 d2, d3
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vtrn.16 d4, d5
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vst1.16 {d2}, [r1]
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vst1.16 {d3}, [r3]
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vst1.16 {d4}, [r12]
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vst1.16 {d5}, [r0]
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bx lr
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ENDP
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;-----------------
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2011-01-24 10:21:40 +01:00
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2010-05-18 17:58:33 +02:00
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idct_coeff
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DCD 0x4e7b4e7b, 0x8a8c8a8c
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;20091, 20091, 35468, 35468
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END
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