vpx/vpx_ports/x86.h

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/*
* Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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*
* Use of this source code is governed by a BSD-style license
* that can be found in the LICENSE file in the root of the source
* tree. An additional intellectual property rights grant can be found
* in the file PATENTS. All contributing project authors may
* be found in the AUTHORS file in the root of the source tree.
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*/
#ifndef VPX_PORTS_X86_H
#define VPX_PORTS_X86_H
#include <stdlib.h>
WebM Experimental Codec Branch Snapshot This is a code snapshot of experimental work currently ongoing for a next-generation codec. The codebase has been cut down considerably from the libvpx baseline. For example, we are currently only supporting VBR 2-pass rate control and have removed most of the code relating to coding speed, threading, error resilience, partitions and various other features. This is in part to make the codebase easier to work on and experiment with, but also because we want to have an open discussion about how the bitstream will be structured and partitioned and not have that conversation constrained by past work. Our basic working pattern has been to initially encapsulate experiments using configure options linked to #IF CONFIG_XXX statements in the code. Once experiments have matured and we are reasonably happy that they give benefit and can be merged without breaking other experiments, we remove the conditional compile statements and merge them in. Current changes include: * Temporal coding experiment for segments (though still only 4 max, it will likely be increased). * Segment feature experiment - to allow various bits of information to be coded at the segment level. Features tested so far include mode and reference frame information, limiting end of block offset and transform size, alongside Q and loop filter parameters, but this set is very fluid. * Support for 8x8 transform - 8x8 dct with 2nd order 2x2 haar is used in MBs using 16x16 prediction modes within inter frames. * Compound prediction (combination of signals from existing predictors to create a new predictor). * 8 tap interpolation filters and 1/8th pel motion vectors. * Loop filter modifications. * Various entropy modifications and changes to how entropy contexts and updates are handled. * Extended quantizer range matched to transform precision improvements. There are also ongoing further experiments that we hope to merge in the near future: For example, coding of motion and other aspects of the prediction signal to better support larger image formats, use of larger block sizes (e.g. 32x32 and up) and lossless non-transform based coding options (especially for key frames). It is our hope that we will be able to make regular updates and we will warmly welcome community contributions. Please be warned that, at this stage, the codebase is currently slower than VP8 stable branch as most new code has not been optimized, and even the 'C' has been deliberately written to be simple and obvious, not fast. The following graphs have the initial test results, numbers in the tables measure the compression improvement in terms of percentage. The build has the following optional experiments configured: --enable-experimental --enable-enhanced_interp --enable-uvintra --enable-high_precision_mv --enable-sixteenth_subpel_uv CIF Size clips: http://getwebm.org/tmp/cif/ HD size clips: http://getwebm.org/tmp/hd/ (stable_20120309 represents encoding results of WebM master branch build as of commit#7a15907) They were encoded using the following encode parameters: --good --cpu-used=0 -t 0 --lag-in-frames=25 --min-q=0 --max-q=63 --end-usage=0 --auto-alt-ref=1 -p 2 --pass=2 --kf-max-dist=9999 --kf-min-dist=0 --drop-frame=0 --static-thresh=0 --bias-pct=50 --minsection-pct=0 --maxsection-pct=800 --sharpness=0 --arnr-maxframes=7 --arnr-strength=3(for HD,6 for CIF) --arnr-type=3 Change-Id: I5c62ed09cfff5815a2bb34e7820d6a810c23183c
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#include "config.h"
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typedef enum {
VPX_CPU_UNKNOWN = -1,
VPX_CPU_AMD,
VPX_CPU_AMD_OLD,
VPX_CPU_CENTAUR,
VPX_CPU_CYRIX,
VPX_CPU_INTEL,
VPX_CPU_NEXGEN,
VPX_CPU_NSC,
VPX_CPU_RISE,
VPX_CPU_SIS,
VPX_CPU_TRANSMETA,
VPX_CPU_TRANSMETA_OLD,
VPX_CPU_UMC,
VPX_CPU_VIA,
VPX_CPU_LAST
} vpx_cpu_t;
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#if defined(__GNUC__) && __GNUC__
#if ARCH_X86_64
#define cpuid(func,ax,bx,cx,dx)\
__asm__ __volatile__ (\
"cpuid \n\t" \
: "=a" (ax), "=b" (bx), "=c" (cx), "=d" (dx) \
: "a" (func));
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#else
#define cpuid(func,ax,bx,cx,dx)\
__asm__ __volatile__ (\
"mov %%ebx, %%edi \n\t" \
"cpuid \n\t" \
"xchg %%edi, %%ebx \n\t" \
: "=a" (ax), "=D" (bx), "=c" (cx), "=d" (dx) \
: "a" (func));
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#endif
#else
#if ARCH_X86_64
void __cpuid(int CPUInfo[4], int info_type);
#pragma intrinsic(__cpuid)
#define cpuid(func,a,b,c,d) do{\
int regs[4];\
__cpuid(regs,func); a=regs[0]; b=regs[1]; c=regs[2]; d=regs[3];\
} while(0)
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#else
#define cpuid(func,a,b,c,d)\
__asm mov eax, func\
__asm cpuid\
__asm mov a, eax\
__asm mov b, ebx\
__asm mov c, ecx\
__asm mov d, edx
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#endif
#endif
#define HAS_MMX 0x01
#define HAS_SSE 0x02
#define HAS_SSE2 0x04
#define HAS_SSE3 0x08
#define HAS_SSSE3 0x10
#define HAS_SSE4_1 0x20
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#ifndef BIT
#define BIT(n) (1<<n)
#endif
static int
x86_simd_caps(void) {
unsigned int flags = 0;
unsigned int mask = ~0;
unsigned int reg_eax, reg_ebx, reg_ecx, reg_edx;
char *env;
(void)reg_ebx;
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/* See if the CPU capabilities are being overridden by the environment */
env = getenv("VPX_SIMD_CAPS");
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if (env && *env)
return (int)strtol(env, NULL, 0);
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env = getenv("VPX_SIMD_CAPS_MASK");
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if (env && *env)
mask = strtol(env, NULL, 0);
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/* Ensure that the CPUID instruction supports extended features */
cpuid(0, reg_eax, reg_ebx, reg_ecx, reg_edx);
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if (reg_eax < 1)
return 0;
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/* Get the standard feature flags */
cpuid(1, reg_eax, reg_ebx, reg_ecx, reg_edx);
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if (reg_edx & BIT(23)) flags |= HAS_MMX;
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if (reg_edx & BIT(25)) flags |= HAS_SSE; /* aka xmm */
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if (reg_edx & BIT(26)) flags |= HAS_SSE2; /* aka wmt */
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if (reg_ecx & BIT(0)) flags |= HAS_SSE3;
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if (reg_ecx & BIT(9)) flags |= HAS_SSSE3;
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if (reg_ecx & BIT(19)) flags |= HAS_SSE4_1;
return flags & mask;
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}
vpx_cpu_t vpx_x86_vendor(void);
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#if ARCH_X86_64 && defined(_MSC_VER)
unsigned __int64 __rdtsc(void);
#pragma intrinsic(__rdtsc)
#endif
static unsigned int
x86_readtsc(void) {
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#if defined(__GNUC__) && __GNUC__
unsigned int tsc;
__asm__ __volatile__("rdtsc\n\t":"=a"(tsc):);
return tsc;
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#else
#if ARCH_X86_64
return __rdtsc();
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#else
__asm rdtsc;
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#endif
#endif
}
#if defined(__GNUC__) && __GNUC__
#define x86_pause_hint()\
__asm__ __volatile__ ("pause \n\t")
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#else
#if ARCH_X86_64
#define x86_pause_hint()\
_mm_pause();
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#else
#define x86_pause_hint()\
__asm pause
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#endif
#endif
#if defined(__GNUC__) && __GNUC__
static void
x87_set_control_word(unsigned short mode) {
__asm__ __volatile__("fldcw %0" : : "m"( *&mode));
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}
static unsigned short
x87_get_control_word(void) {
unsigned short mode;
__asm__ __volatile__("fstcw %0\n\t":"=m"( *&mode):);
return mode;
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}
#elif ARCH_X86_64
/* No fldcw intrinsics on Windows x64, punt to external asm */
extern void vpx_winx64_fldcw(unsigned short mode);
extern unsigned short vpx_winx64_fstcw(void);
#define x87_set_control_word vpx_winx64_fldcw
#define x87_get_control_word vpx_winx64_fstcw
#else
static void
x87_set_control_word(unsigned short mode) {
__asm { fldcw mode }
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}
static unsigned short
x87_get_control_word(void) {
unsigned short mode;
__asm { fstcw mode }
return mode;
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}
#endif
static unsigned short
x87_set_double_precision(void) {
unsigned short mode = x87_get_control_word();
x87_set_control_word((mode&~0x300) | 0x200);
return mode;
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}
extern void vpx_reset_mmx_state(void);
#endif