2010-05-18 17:58:33 +02:00
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; Copyright (c) 2010 The VP8 project authors. All Rights Reserved.
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;
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2010-06-18 18:39:21 +02:00
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; Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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; in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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; be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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;
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%include "vpx_ports/x86_abi_support.asm"
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global sym(vp8_short_fdct4x4_wmt)
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%define DCTCONSTANTSBITS (16)
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%define DCTROUNDINGVALUE (1<< (DCTCONSTANTSBITS-1))
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%define x_c1 (60547) ; cos(pi /8) * (1<<15)
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%define x_c2 (46341) ; cos(pi*2/8) * (1<<15)
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%define x_c3 (25080) ; cos(pi*3/8) * (1<<15)
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%define _1STSTAGESHIFT 14
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%define _2NDSTAGESHIFT 16
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;; using matrix multiply
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;void vp8_short_fdct4x4_wmt(short *input, short *output)
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sym(vp8_short_fdct4x4_wmt):
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push rbp
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mov rbp, rsp
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SHADOW_ARGS_TO_STACK 2
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GET_GOT rbx
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; end prolog
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mov rax, arg(0) ;input
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mov rcx, arg(1) ;output
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lea rdx, [dct_matrix_sse2 GLOBAL]
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movdqu xmm0, [rax ]
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movdqu xmm1, [rax+16]
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; first column
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movdqa xmm2, xmm0
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movdqa xmm7, [rdx]
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pmaddwd xmm2, xmm7
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movdqa xmm3, xmm1
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pmaddwd xmm3, xmm7
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movdqa xmm4, xmm2
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punpckldq xmm2, xmm3
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punpckhdq xmm4, xmm3
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movdqa xmm3, xmm2
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punpckldq xmm2, xmm4
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punpckhdq xmm3, xmm4
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paddd xmm2, xmm3
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paddd xmm2, XMMWORD PTR [dct1st_stage_rounding_sse2 GLOBAL]
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psrad xmm2, _1STSTAGESHIFT
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;second column
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movdqa xmm3, xmm0
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pmaddwd xmm3, [rdx+16]
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movdqa xmm4, xmm1
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pmaddwd xmm4, [rdx+16]
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movdqa xmm5, xmm3
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punpckldq xmm3, xmm4
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punpckhdq xmm5, xmm4
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movdqa xmm4, xmm3
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punpckldq xmm3, xmm5
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punpckhdq xmm4, xmm5
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paddd xmm3, xmm4
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paddd xmm3, XMMWORD PTR [dct1st_stage_rounding_sse2 GLOBAL]
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psrad xmm3, _1STSTAGESHIFT
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packssdw xmm2, xmm3
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;third column
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movdqa xmm3, xmm0
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pmaddwd xmm3, [rdx+32]
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movdqa xmm4, xmm1
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pmaddwd xmm4, [rdx+32]
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movdqa xmm5, xmm3
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punpckldq xmm3, xmm4
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punpckhdq xmm5, xmm4
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movdqa xmm4, xmm3
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punpckldq xmm3, xmm5
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punpckhdq xmm4, xmm5
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paddd xmm3, xmm4
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paddd xmm3, XMMWORD PTR [dct1st_stage_rounding_sse2 GLOBAL]
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psrad xmm3, _1STSTAGESHIFT
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;fourth column (this is the last column, so we do not have save the source any more)
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pmaddwd xmm0, [rdx+48]
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pmaddwd xmm1, [rdx+48]
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movdqa xmm4, xmm0
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punpckldq xmm0, xmm1
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punpckhdq xmm4, xmm1
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movdqa xmm1, xmm0
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punpckldq xmm0, xmm4
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punpckhdq xmm1, xmm4
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paddd xmm0, xmm1
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paddd xmm0, XMMWORD PTR [dct1st_stage_rounding_sse2 GLOBAL]
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psrad xmm0, _1STSTAGESHIFT
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packssdw xmm3, xmm0
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; done with one pass
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; now start second pass
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movdqa xmm0, xmm2
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movdqa xmm1, xmm3
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pmaddwd xmm2, xmm7
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pmaddwd xmm3, xmm7
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movdqa xmm4, xmm2
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punpckldq xmm2, xmm3
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punpckhdq xmm4, xmm3
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movdqa xmm3, xmm2
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punpckldq xmm2, xmm4
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punpckhdq xmm3, xmm4
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paddd xmm2, xmm3
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paddd xmm2, XMMWORD PTR [dct2nd_stage_rounding_sse2 GLOBAL]
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psrad xmm2, _2NDSTAGESHIFT
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;second column
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movdqa xmm3, xmm0
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pmaddwd xmm3, [rdx+16]
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movdqa xmm4, xmm1
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pmaddwd xmm4, [rdx+16]
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movdqa xmm5, xmm3
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punpckldq xmm3, xmm4
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punpckhdq xmm5, xmm4
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movdqa xmm4, xmm3
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punpckldq xmm3, xmm5
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punpckhdq xmm4, xmm5
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paddd xmm3, xmm4
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paddd xmm3, XMMWORD PTR [dct2nd_stage_rounding_sse2 GLOBAL]
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psrad xmm3, _2NDSTAGESHIFT
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packssdw xmm2, xmm3
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movdqu [rcx], xmm2
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;third column
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movdqa xmm3, xmm0
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pmaddwd xmm3, [rdx+32]
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movdqa xmm4, xmm1
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pmaddwd xmm4, [rdx+32]
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movdqa xmm5, xmm3
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punpckldq xmm3, xmm4
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punpckhdq xmm5, xmm4
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movdqa xmm4, xmm3
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punpckldq xmm3, xmm5
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punpckhdq xmm4, xmm5
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paddd xmm3, xmm4
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paddd xmm3, XMMWORD PTR [dct2nd_stage_rounding_sse2 GLOBAL]
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psrad xmm3, _2NDSTAGESHIFT
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;fourth column
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pmaddwd xmm0, [rdx+48]
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pmaddwd xmm1, [rdx+48]
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movdqa xmm4, xmm0
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punpckldq xmm0, xmm1
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punpckhdq xmm4, xmm1
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movdqa xmm1, xmm0
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punpckldq xmm0, xmm4
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punpckhdq xmm1, xmm4
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paddd xmm0, xmm1
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paddd xmm0, XMMWORD PTR [dct2nd_stage_rounding_sse2 GLOBAL]
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psrad xmm0, _2NDSTAGESHIFT
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packssdw xmm3, xmm0
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movdqu [rcx+16], xmm3
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mov rsp, rbp
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; begin epilog
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RESTORE_GOT
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UNSHADOW_ARGS
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pop rbp
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ret
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SECTION_RODATA
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;static unsigned int dct1st_stage_rounding_sse2[4] =
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align 16
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dct1st_stage_rounding_sse2:
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times 4 dd 8192
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;static unsigned int dct2nd_stage_rounding_sse2[4] =
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align 16
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dct2nd_stage_rounding_sse2:
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times 4 dd 32768
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;static short dct_matrix_sse2[4][8]=
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align 16
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dct_matrix_sse2:
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times 8 dw 23170
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dw 30274
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dw 12540
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dw -12540
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dw -30274
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dw 30274
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dw 12540
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dw -12540
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dw -30274
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dw 23170
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times 2 dw -23170
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times 2 dw 23170
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times 2 dw -23170
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dw 23170
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dw 12540
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dw -30274
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dw 30274
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dw -12540
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dw 12540
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dw -30274
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dw 30274
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dw -12540
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