2010-05-18 17:58:33 +02:00
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/*
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2010-09-09 14:16:39 +02:00
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* Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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2010-05-18 17:58:33 +02:00
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*
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2010-06-18 18:39:21 +02:00
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* Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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* in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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* be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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*/
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#include "vpx_ports/config.h"
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2011-02-10 20:41:38 +01:00
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#include "vp8/common/g_common.h"
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#include "vp8/common/subpixel.h"
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#include "vp8/common/loopfilter.h"
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#include "vp8/common/recon.h"
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#include "vp8/common/idct.h"
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#include "vp8/common/onyxc_int.h"
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2010-05-18 17:58:33 +02:00
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extern void vp8_arch_x86_common_init(VP8_COMMON *ctx);
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Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
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extern void vp8_arch_arm_common_init(VP8_COMMON *ctx);
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2010-05-18 17:58:33 +02:00
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void vp8_machine_specific_config(VP8_COMMON *ctx)
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{
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#if CONFIG_RUNTIME_CPU_DETECT
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VP8_COMMON_RTCD *rtcd = &ctx->rtcd;
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rtcd->idct.idct1 = vp8_short_idct4x4llm_1_c;
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rtcd->idct.idct16 = vp8_short_idct4x4llm_c;
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2010-05-28 20:28:12 +02:00
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rtcd->idct.idct1_scalar_add = vp8_dc_only_idct_add_c;
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2010-05-18 17:58:33 +02:00
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rtcd->idct.iwalsh1 = vp8_short_inv_walsh4x4_1_c;
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rtcd->idct.iwalsh16 = vp8_short_inv_walsh4x4_c;
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2011-02-14 23:18:18 +01:00
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#if CONFIG_T8X8
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rtcd->idct.idct8 = vp8_short_idct8x8_c;
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rtcd->idct.idct8_1 = vp8_short_idct8x8_1_c;
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rtcd->idct.idct1_scalar_add_8x8 = vp8_dc_only_idct_add_8x8_c;
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rtcd->idct.ihaar2 = vp8_short_ihaar2x2_c;
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rtcd->idct.ihaar2_1 = vp8_short_ihaar2x2_1_c;
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#endif
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2010-05-18 17:58:33 +02:00
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rtcd->recon.copy16x16 = vp8_copy_mem16x16_c;
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rtcd->recon.copy8x8 = vp8_copy_mem8x8_c;
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Dual 16x16 inter prediction.
This patch introduces the concept of dual inter16x16 prediction. A
16x16 inter-predicted macroblock can use 2 references instead of 1,
where both references use the same mvmode (new, near/est, zero). In the
case of newmv, this means that two MVs are coded instead of one. The
frame can be encoded in 3 ways: all MBs single-prediction, all MBs dual
prediction, or per-MB single/dual prediction selection ("hybrid"), in
which case a single bit is coded per-MB to indicate whether the MB uses
single or dual inter prediction.
In the future, we can (maybe?) get further gains by mixing this with
Adrian's 32x32 work, per-segment dual prediction settings, or adding
support for dual splitmv/8x8mv inter prediction.
Gain (on derf-set, CQ mode) is ~2.8% (SSIM) or ~3.6% (glb PSNR). Most
gain is at medium/high bitrates, but there's minor gains at low bitrates
also. Output was confirmed to match between encoder and decoder.
Note for optimization people: this patch introduces a 2nd version of
16x16/8x8 sixtap/bilin functions, which does an avg instead of a
store. They may want to look and make sure this is implemented to
their satisfaction so we can optimize it best in the future.
Change-ID: I59dc84b07cbb3ccf073ac0f756d03d294cb19281
2011-12-06 20:53:02 +01:00
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rtcd->recon.avg16x16 = vp8_avg_mem16x16_c;
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rtcd->recon.avg8x8 = vp8_avg_mem8x8_c;
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2010-05-18 17:58:33 +02:00
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rtcd->recon.copy8x4 = vp8_copy_mem8x4_c;
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2010-10-26 17:37:23 +02:00
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rtcd->recon.recon = vp8_recon_b_c;
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2011-08-05 01:30:27 +02:00
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rtcd->recon.recon_uv = vp8_recon_uv_b_c;
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2010-05-18 17:58:33 +02:00
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rtcd->recon.recon2 = vp8_recon2b_c;
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2010-10-26 17:37:23 +02:00
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rtcd->recon.recon4 = vp8_recon4b_c;
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rtcd->recon.recon_mb = vp8_recon_mb_c;
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rtcd->recon.recon_mby = vp8_recon_mby_c;
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2011-03-11 17:35:38 +01:00
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rtcd->recon.build_intra_predictors_mby =
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vp8_build_intra_predictors_mby;
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rtcd->recon.build_intra_predictors_mby_s =
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vp8_build_intra_predictors_mby_s;
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2011-04-27 19:05:10 +02:00
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rtcd->recon.build_intra_predictors_mbuv =
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vp8_build_intra_predictors_mbuv;
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rtcd->recon.build_intra_predictors_mbuv_s =
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vp8_build_intra_predictors_mbuv_s;
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rtcd->recon.intra4x4_predict =
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vp8_intra4x4_predict;
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2011-08-05 01:30:27 +02:00
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rtcd->recon.intra8x8_predict =
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vp8_intra8x8_predict;
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rtcd->recon.intra_uv4x4_predict =
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vp8_intra_uv4x4_predict;
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Dual 16x16 inter prediction.
This patch introduces the concept of dual inter16x16 prediction. A
16x16 inter-predicted macroblock can use 2 references instead of 1,
where both references use the same mvmode (new, near/est, zero). In the
case of newmv, this means that two MVs are coded instead of one. The
frame can be encoded in 3 ways: all MBs single-prediction, all MBs dual
prediction, or per-MB single/dual prediction selection ("hybrid"), in
which case a single bit is coded per-MB to indicate whether the MB uses
single or dual inter prediction.
In the future, we can (maybe?) get further gains by mixing this with
Adrian's 32x32 work, per-segment dual prediction settings, or adding
support for dual splitmv/8x8mv inter prediction.
Gain (on derf-set, CQ mode) is ~2.8% (SSIM) or ~3.6% (glb PSNR). Most
gain is at medium/high bitrates, but there's minor gains at low bitrates
also. Output was confirmed to match between encoder and decoder.
Note for optimization people: this patch introduces a 2nd version of
16x16/8x8 sixtap/bilin functions, which does an avg instead of a
store. They may want to look and make sure this is implemented to
their satisfaction so we can optimize it best in the future.
Change-ID: I59dc84b07cbb3ccf073ac0f756d03d294cb19281
2011-12-06 20:53:02 +01:00
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rtcd->subpix.sixtap16x16 = vp8_sixtap_predict16x16_c;
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rtcd->subpix.sixtap8x8 = vp8_sixtap_predict8x8_c;
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rtcd->subpix.sixtap_avg16x16 = vp8_sixtap_predict_avg16x16_c;
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rtcd->subpix.sixtap_avg8x8 = vp8_sixtap_predict_avg8x8_c;
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rtcd->subpix.sixtap8x4 = vp8_sixtap_predict8x4_c;
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rtcd->subpix.sixtap4x4 = vp8_sixtap_predict_c;
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rtcd->subpix.bilinear16x16 = vp8_bilinear_predict16x16_c;
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rtcd->subpix.bilinear8x8 = vp8_bilinear_predict8x8_c;
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rtcd->subpix.bilinear_avg16x16 = vp8_bilinear_predict_avg16x16_c;
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rtcd->subpix.bilinear_avg8x8 = vp8_bilinear_predict_avg8x8_c;
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rtcd->subpix.bilinear8x4 = vp8_bilinear_predict8x4_c;
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rtcd->subpix.bilinear4x4 = vp8_bilinear_predict4x4_c;
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2010-05-18 17:58:33 +02:00
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rtcd->loopfilter.normal_mb_v = vp8_loop_filter_mbv_c;
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rtcd->loopfilter.normal_b_v = vp8_loop_filter_bv_c;
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rtcd->loopfilter.normal_mb_h = vp8_loop_filter_mbh_c;
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rtcd->loopfilter.normal_b_h = vp8_loop_filter_bh_c;
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2011-06-10 13:10:21 +02:00
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rtcd->loopfilter.simple_mb_v = vp8_loop_filter_simple_vertical_edge_c;
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2010-05-18 17:58:33 +02:00
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rtcd->loopfilter.simple_b_v = vp8_loop_filter_bvs_c;
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2011-06-10 13:10:21 +02:00
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rtcd->loopfilter.simple_mb_h = vp8_loop_filter_simple_horizontal_edge_c;
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2010-05-18 17:58:33 +02:00
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rtcd->loopfilter.simple_b_h = vp8_loop_filter_bhs_c;
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2011-04-29 18:37:59 +02:00
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#if CONFIG_POSTPROC || (CONFIG_VP8_ENCODER && CONFIG_INTERNAL_STATS)
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2010-11-04 18:35:02 +01:00
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rtcd->postproc.down = vp8_mbpost_proc_down_c;
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rtcd->postproc.across = vp8_mbpost_proc_across_ip_c;
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rtcd->postproc.downacross = vp8_post_proc_down_and_across_c;
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rtcd->postproc.addnoise = vp8_plane_add_noise_c;
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rtcd->postproc.blend_mb_inner = vp8_blend_mb_inner_c;
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rtcd->postproc.blend_mb_outer = vp8_blend_mb_outer_c;
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rtcd->postproc.blend_b = vp8_blend_b_c;
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2010-05-18 17:58:33 +02:00
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#endif
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#endif
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#if ARCH_X86 || ARCH_X86_64
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vp8_arch_x86_common_init(ctx);
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#endif
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2010-12-02 00:50:14 +01:00
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Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
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#if ARCH_ARM
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vp8_arch_arm_common_init(ctx);
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#endif
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2010-12-02 00:50:14 +01:00
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rtcd->idct.idct1 = vp8_short_idct4x4llm_1_c;
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rtcd->idct.idct16 = vp8_short_idct4x4llm_c;
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rtcd->idct.idct1_scalar_add = vp8_dc_only_idct_add_c;
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rtcd->idct.iwalsh1 = vp8_short_inv_walsh4x4_1_c;
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rtcd->idct.iwalsh16 = vp8_short_inv_walsh4x4_c;
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2010-05-18 17:58:33 +02:00
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}
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