2010-05-18 17:58:33 +02:00
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2010-09-09 14:16:39 +02:00
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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2010-05-18 17:58:33 +02:00
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;
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2010-06-18 18:39:21 +02:00
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; Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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; in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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; be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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;
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.globl vp8_sad16x16_ppc
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.globl vp8_sad16x8_ppc
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.globl vp8_sad8x16_ppc
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.globl vp8_sad8x8_ppc
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.globl vp8_sad4x4_ppc
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.macro load_aligned_16 V R O
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lvsl v3, 0, \R ;# permutate value for alignment
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lvx v1, 0, \R
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lvx v2, \O, \R
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vperm \V, v1, v2, v3
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.endm
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.macro prologue
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mfspr r11, 256 ;# get old VRSAVE
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oris r12, r11, 0xffc0
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mtspr 256, r12 ;# set VRSAVE
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stwu r1, -32(r1) ;# create space on the stack
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li r10, 16 ;# load offset and loop counter
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vspltisw v8, 0 ;# zero out total to start
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.endm
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.macro epilogue
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addi r1, r1, 32 ;# recover stack
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mtspr 256, r11 ;# reset old VRSAVE
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.endm
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.macro SAD_16
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;# v6 = abs (v4 - v5)
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vsububs v6, v4, v5
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vsububs v7, v5, v4
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vor v6, v6, v7
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;# v8 += abs (v4 - v5)
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vsum4ubs v8, v6, v8
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.endm
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.macro sad_16_loop loop_label
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lvsl v3, 0, r5 ;# only needs to be done once per block
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;# preload a line of data before getting into the loop
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lvx v4, 0, r3
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lvx v1, 0, r5
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lvx v2, r10, r5
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add r5, r5, r6
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add r3, r3, r4
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vperm v5, v1, v2, v3
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.align 4
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\loop_label:
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;# compute difference on first row
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vsububs v6, v4, v5
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vsububs v7, v5, v4
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;# load up next set of data
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lvx v9, 0, r3
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lvx v1, 0, r5
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lvx v2, r10, r5
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;# perform abs() of difference
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vor v6, v6, v7
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add r3, r3, r4
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;# add to the running tally
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vsum4ubs v8, v6, v8
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;# now onto the next line
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vperm v5, v1, v2, v3
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add r5, r5, r6
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lvx v4, 0, r3
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;# compute difference on second row
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vsububs v6, v9, v5
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lvx v1, 0, r5
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vsububs v7, v5, v9
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lvx v2, r10, r5
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vor v6, v6, v7
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add r3, r3, r4
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vsum4ubs v8, v6, v8
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vperm v5, v1, v2, v3
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add r5, r5, r6
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bdnz \loop_label
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vspltisw v7, 0
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vsumsws v8, v8, v7
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stvx v8, 0, r1
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lwz r3, 12(r1)
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.endm
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.macro sad_8_loop loop_label
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.align 4
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\loop_label:
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;# only one of the inputs should need to be aligned.
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load_aligned_16 v4, r3, r10
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load_aligned_16 v5, r5, r10
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;# move onto the next line
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add r3, r3, r4
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add r5, r5, r6
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;# only one of the inputs should need to be aligned.
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load_aligned_16 v6, r3, r10
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load_aligned_16 v7, r5, r10
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;# move onto the next line
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add r3, r3, r4
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add r5, r5, r6
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vmrghb v4, v4, v6
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vmrghb v5, v5, v7
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SAD_16
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bdnz \loop_label
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vspltisw v7, 0
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vsumsws v8, v8, v7
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stvx v8, 0, r1
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lwz r3, 12(r1)
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.endm
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.align 2
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;# r3 unsigned char *src_ptr
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;# r4 int src_stride
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;# r5 unsigned char *ref_ptr
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;# r6 int ref_stride
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;#
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;# r3 return value
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vp8_sad16x16_ppc:
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prologue
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li r9, 8
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mtctr r9
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sad_16_loop sad16x16_loop
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epilogue
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blr
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.align 2
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;# r3 unsigned char *src_ptr
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;# r4 int src_stride
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;# r5 unsigned char *ref_ptr
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;# r6 int ref_stride
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;#
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;# r3 return value
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vp8_sad16x8_ppc:
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prologue
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li r9, 4
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mtctr r9
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sad_16_loop sad16x8_loop
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epilogue
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blr
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.align 2
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;# r3 unsigned char *src_ptr
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;# r4 int src_stride
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;# r5 unsigned char *ref_ptr
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;# r6 int ref_stride
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;#
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;# r3 return value
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vp8_sad8x16_ppc:
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prologue
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li r9, 8
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mtctr r9
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sad_8_loop sad8x16_loop
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epilogue
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blr
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.align 2
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;# r3 unsigned char *src_ptr
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;# r4 int src_stride
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;# r5 unsigned char *ref_ptr
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;# r6 int ref_stride
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;#
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;# r3 return value
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vp8_sad8x8_ppc:
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prologue
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li r9, 4
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mtctr r9
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sad_8_loop sad8x8_loop
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epilogue
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blr
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.macro transfer_4x4 I P
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lwz r0, 0(\I)
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add \I, \I, \P
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lwz r7, 0(\I)
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add \I, \I, \P
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lwz r8, 0(\I)
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add \I, \I, \P
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lwz r9, 0(\I)
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stw r0, 0(r1)
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stw r7, 4(r1)
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stw r8, 8(r1)
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stw r9, 12(r1)
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.endm
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.align 2
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;# r3 unsigned char *src_ptr
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;# r4 int src_stride
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;# r5 unsigned char *ref_ptr
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;# r6 int ref_stride
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;#
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;# r3 return value
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vp8_sad4x4_ppc:
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prologue
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transfer_4x4 r3, r4
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lvx v4, 0, r1
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transfer_4x4 r5, r6
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lvx v5, 0, r1
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vspltisw v8, 0 ;# zero out total to start
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;# v6 = abs (v4 - v5)
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vsububs v6, v4, v5
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vsububs v7, v5, v4
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vor v6, v6, v7
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;# v8 += abs (v4 - v5)
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vsum4ubs v7, v6, v8
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vsumsws v7, v7, v8
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stvx v7, 0, r1
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lwz r3, 12(r1)
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epilogue
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blr
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