2010-05-18 17:58:33 +02:00
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;
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2010-09-09 14:16:39 +02:00
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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2010-05-18 17:58:33 +02:00
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;
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2010-06-18 18:39:21 +02:00
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; Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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; in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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; be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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;
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EXPORT |vp8_start_encode|
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EXPORT |vp8_encode_bool|
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EXPORT |vp8_stop_encode|
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EXPORT |vp8_encode_value|
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2011-11-10 12:07:37 +01:00
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IMPORT |vp8_validate_buffer_arm|
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2010-05-18 17:58:33 +02:00
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2011-02-04 23:44:31 +01:00
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INCLUDE asm_enc_offsets.asm
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2010-05-18 17:58:33 +02:00
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ARM
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REQUIRE8
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PRESERVE8
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AREA |.text|, CODE, READONLY
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2011-11-10 12:07:37 +01:00
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; macro for validating write buffer position
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; needs vp8_writer in r0
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; start shall not be in r1
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MACRO
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VALIDATE_POS $start, $pos
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push {r0-r3, r12, lr} ; rest of regs are preserved by subroutine call
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ldr r2, [r0, #vp8_writer_buffer_end]
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ldr r3, [r0, #vp8_writer_error]
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mov r1, $pos
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mov r0, $start
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bl vp8_validate_buffer_arm
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pop {r0-r3, r12, lr}
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MEND
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2010-05-18 17:58:33 +02:00
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; r0 BOOL_CODER *br
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; r1 unsigned char *source
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2011-10-27 08:06:45 +02:00
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; r2 unsigned char *source_end
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2010-05-18 17:58:33 +02:00
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|vp8_start_encode| PROC
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2011-10-27 08:06:45 +02:00
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str r2, [r0, #vp8_writer_buffer_end]
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2010-05-18 17:58:33 +02:00
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mov r12, #0
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mov r3, #255
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mvn r2, #23
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str r12, [r0, #vp8_writer_lowvalue]
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str r3, [r0, #vp8_writer_range]
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str r12, [r0, #vp8_writer_value]
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str r2, [r0, #vp8_writer_count]
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str r12, [r0, #vp8_writer_pos]
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str r1, [r0, #vp8_writer_buffer]
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bx lr
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ENDP
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; r0 BOOL_CODER *br
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; r1 int bit
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; r2 int probability
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|vp8_encode_bool| PROC
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2011-11-10 12:07:37 +01:00
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push {r4-r10, lr}
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2010-05-18 17:58:33 +02:00
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mov r4, r2
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ldr r2, [r0, #vp8_writer_lowvalue]
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ldr r5, [r0, #vp8_writer_range]
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ldr r3, [r0, #vp8_writer_count]
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sub r7, r5, #1 ; range-1
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cmp r1, #0
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2011-09-19 09:59:52 +02:00
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mul r6, r4, r7 ; ((range-1) * probability)
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2010-05-18 17:58:33 +02:00
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mov r7, #1
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2011-09-19 09:59:52 +02:00
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add r4, r7, r6, lsr #8 ; 1 + (((range-1) * probability) >> 8)
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2010-05-18 17:58:33 +02:00
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addne r2, r2, r4 ; if (bit) lowvalue += split
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subne r4, r5, r4 ; if (bit) range = range-split
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; Counting the leading zeros is used to normalize range.
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clz r6, r4
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sub r6, r6, #24 ; shift
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; Flag is set on the sum of count. This flag is used later
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; to determine if count >= 0
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adds r3, r3, r6 ; count += shift
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lsl r5, r4, r6 ; range <<= shift
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bmi token_count_lt_zero ; if(count >= 0)
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sub r6, r6, r3 ; offset = shift - count
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sub r4, r6, #1 ; offset-1
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lsls r4, r2, r4 ; if((lowvalue<<(offset-1)) & 0x80000000 )
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bpl token_high_bit_not_set
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ldr r4, [r0, #vp8_writer_pos] ; x
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sub r4, r4, #1 ; x = w->pos-1
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b token_zero_while_start
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token_zero_while_loop
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mov r9, #0
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strb r9, [r7, r4] ; w->buffer[x] =(unsigned char)0
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sub r4, r4, #1 ; x--
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token_zero_while_start
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cmp r4, #0
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ldrge r7, [r0, #vp8_writer_buffer]
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ldrb r1, [r7, r4]
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cmpge r1, #0xff
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beq token_zero_while_loop
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ldr r7, [r0, #vp8_writer_buffer]
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ldrb r9, [r7, r4] ; w->buffer[x]
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add r9, r9, #1
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strb r9, [r7, r4] ; w->buffer[x] + 1
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token_high_bit_not_set
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rsb r4, r6, #24 ; 24-offset
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ldr r9, [r0, #vp8_writer_buffer]
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lsr r7, r2, r4 ; lowvalue >> (24-offset)
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ldr r4, [r0, #vp8_writer_pos] ; w->pos
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lsl r2, r2, r6 ; lowvalue <<= offset
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mov r6, r3 ; shift = count
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add r1, r4, #1 ; w->pos++
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bic r2, r2, #0xff000000 ; lowvalue &= 0xffffff
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str r1, [r0, #vp8_writer_pos]
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sub r3, r3, #8 ; count -= 8
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2011-11-10 12:07:37 +01:00
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VALIDATE_POS r9, r1 ; validate_buffer at pos
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2010-05-18 17:58:33 +02:00
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strb r7, [r9, r4] ; w->buffer[w->pos++]
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token_count_lt_zero
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lsl r2, r2, r6 ; lowvalue <<= shift
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str r2, [r0, #vp8_writer_lowvalue]
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str r5, [r0, #vp8_writer_range]
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str r3, [r0, #vp8_writer_count]
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2011-11-10 12:07:37 +01:00
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pop {r4-r10, pc}
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2010-05-18 17:58:33 +02:00
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ENDP
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; r0 BOOL_CODER *br
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|vp8_stop_encode| PROC
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push {r4-r10, lr}
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ldr r2, [r0, #vp8_writer_lowvalue]
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ldr r5, [r0, #vp8_writer_range]
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ldr r3, [r0, #vp8_writer_count]
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mov r10, #32
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stop_encode_loop
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sub r7, r5, #1 ; range-1
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mov r4, r7, lsl #7 ; ((range-1) * 128)
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mov r7, #1
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add r4, r7, r4, lsr #8 ; 1 + (((range-1) * 128) >> 8)
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; Counting the leading zeros is used to normalize range.
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clz r6, r4
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sub r6, r6, #24 ; shift
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; Flag is set on the sum of count. This flag is used later
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; to determine if count >= 0
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adds r3, r3, r6 ; count += shift
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lsl r5, r4, r6 ; range <<= shift
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bmi token_count_lt_zero_se ; if(count >= 0)
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sub r6, r6, r3 ; offset = shift - count
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sub r4, r6, #1 ; offset-1
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lsls r4, r2, r4 ; if((lowvalue<<(offset-1)) & 0x80000000 )
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bpl token_high_bit_not_set_se
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ldr r4, [r0, #vp8_writer_pos] ; x
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sub r4, r4, #1 ; x = w->pos-1
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b token_zero_while_start_se
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token_zero_while_loop_se
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mov r9, #0
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strb r9, [r7, r4] ; w->buffer[x] =(unsigned char)0
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sub r4, r4, #1 ; x--
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token_zero_while_start_se
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cmp r4, #0
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ldrge r7, [r0, #vp8_writer_buffer]
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ldrb r1, [r7, r4]
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cmpge r1, #0xff
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beq token_zero_while_loop_se
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ldr r7, [r0, #vp8_writer_buffer]
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ldrb r9, [r7, r4] ; w->buffer[x]
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add r9, r9, #1
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strb r9, [r7, r4] ; w->buffer[x] + 1
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token_high_bit_not_set_se
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rsb r4, r6, #24 ; 24-offset
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ldr r9, [r0, #vp8_writer_buffer]
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lsr r7, r2, r4 ; lowvalue >> (24-offset)
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ldr r4, [r0, #vp8_writer_pos] ; w->pos
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lsl r2, r2, r6 ; lowvalue <<= offset
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mov r6, r3 ; shift = count
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add r1, r4, #1 ; w->pos++
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bic r2, r2, #0xff000000 ; lowvalue &= 0xffffff
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str r1, [r0, #vp8_writer_pos]
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sub r3, r3, #8 ; count -= 8
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2011-11-10 12:07:37 +01:00
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VALIDATE_POS r9, r1 ; validate_buffer at pos
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2010-05-18 17:58:33 +02:00
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strb r7, [r9, r4] ; w->buffer[w->pos++]
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token_count_lt_zero_se
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lsl r2, r2, r6 ; lowvalue <<= shift
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subs r10, r10, #1
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bne stop_encode_loop
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str r2, [r0, #vp8_writer_lowvalue]
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str r5, [r0, #vp8_writer_range]
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str r3, [r0, #vp8_writer_count]
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pop {r4-r10, pc}
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ENDP
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; r0 BOOL_CODER *br
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; r1 int data
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; r2 int bits
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|vp8_encode_value| PROC
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2011-11-10 12:07:37 +01:00
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push {r4-r12, lr}
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2010-05-18 17:58:33 +02:00
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mov r10, r2
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ldr r2, [r0, #vp8_writer_lowvalue]
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ldr r5, [r0, #vp8_writer_range]
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ldr r3, [r0, #vp8_writer_count]
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rsb r4, r10, #32 ; 32-n
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; v is kept in r1 during the token pack loop
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Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
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lsl r1, r1, r4 ; r1 = v << 32 - n
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2010-05-18 17:58:33 +02:00
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encode_value_loop
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sub r7, r5, #1 ; range-1
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; Decisions are made based on the bit value shifted
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; off of v, so set a flag here based on this.
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; This value is refered to as "bb"
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Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
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lsls r1, r1, #1 ; bit = v >> n
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2010-05-18 17:58:33 +02:00
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mov r4, r7, lsl #7 ; ((range-1) * 128)
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mov r7, #1
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add r4, r7, r4, lsr #8 ; 1 + (((range-1) * 128) >> 8)
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addcs r2, r2, r4 ; if (bit) lowvalue += split
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subcs r4, r5, r4 ; if (bit) range = range-split
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; Counting the leading zeros is used to normalize range.
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clz r6, r4
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sub r6, r6, #24 ; shift
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; Flag is set on the sum of count. This flag is used later
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; to determine if count >= 0
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adds r3, r3, r6 ; count += shift
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lsl r5, r4, r6 ; range <<= shift
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bmi token_count_lt_zero_ev ; if(count >= 0)
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sub r6, r6, r3 ; offset = shift - count
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sub r4, r6, #1 ; offset-1
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lsls r4, r2, r4 ; if((lowvalue<<(offset-1)) & 0x80000000 )
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bpl token_high_bit_not_set_ev
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ldr r4, [r0, #vp8_writer_pos] ; x
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sub r4, r4, #1 ; x = w->pos-1
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b token_zero_while_start_ev
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token_zero_while_loop_ev
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mov r9, #0
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strb r9, [r7, r4] ; w->buffer[x] =(unsigned char)0
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sub r4, r4, #1 ; x--
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token_zero_while_start_ev
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cmp r4, #0
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ldrge r7, [r0, #vp8_writer_buffer]
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ldrb r11, [r7, r4]
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cmpge r11, #0xff
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beq token_zero_while_loop_ev
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ldr r7, [r0, #vp8_writer_buffer]
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ldrb r9, [r7, r4] ; w->buffer[x]
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add r9, r9, #1
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strb r9, [r7, r4] ; w->buffer[x] + 1
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token_high_bit_not_set_ev
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rsb r4, r6, #24 ; 24-offset
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ldr r9, [r0, #vp8_writer_buffer]
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lsr r7, r2, r4 ; lowvalue >> (24-offset)
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ldr r4, [r0, #vp8_writer_pos] ; w->pos
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lsl r2, r2, r6 ; lowvalue <<= offset
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mov r6, r3 ; shift = count
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add r11, r4, #1 ; w->pos++
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bic r2, r2, #0xff000000 ; lowvalue &= 0xffffff
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str r11, [r0, #vp8_writer_pos]
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sub r3, r3, #8 ; count -= 8
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2011-11-10 12:07:37 +01:00
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VALIDATE_POS r9, r11 ; validate_buffer at pos
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2010-05-18 17:58:33 +02:00
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strb r7, [r9, r4] ; w->buffer[w->pos++]
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token_count_lt_zero_ev
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lsl r2, r2, r6 ; lowvalue <<= shift
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subs r10, r10, #1
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bne encode_value_loop
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str r2, [r0, #vp8_writer_lowvalue]
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str r5, [r0, #vp8_writer_range]
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str r3, [r0, #vp8_writer_count]
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2011-11-10 12:07:37 +01:00
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pop {r4-r12, pc}
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2010-05-18 17:58:33 +02:00
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ENDP
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END
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