2010-05-18 17:58:33 +02:00
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/*
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2010-09-09 14:16:39 +02:00
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* Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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2010-05-18 17:58:33 +02:00
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*
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2010-06-18 18:39:21 +02:00
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* Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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* in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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* be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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*/
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#ifndef VARIANCE_ARM_H
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#define VARIANCE_ARM_H
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2011-02-09 15:34:56 +01:00
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#if HAVE_ARMV6
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2011-02-10 15:41:22 +01:00
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extern prototype_sad(vp8_sad16x16_armv6);
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2011-02-09 15:34:56 +01:00
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extern prototype_variance(vp8_variance16x16_armv6);
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extern prototype_subpixvariance(vp8_sub_pixel_variance16x16_armv6);
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#if !CONFIG_RUNTIME_CPU_DETECT
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2011-02-10 15:41:22 +01:00
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#undef vp8_variance_sad16x16
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#define vp8_variance_sad16x16 vp8_sad16x16_armv6
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2011-02-09 15:34:56 +01:00
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#undef vp8_variance_subpixvar16x16
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#define vp8_variance_subpixvar16x16 vp8_sub_pixel_variance16x16_armv6
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#undef vp8_variance_var16x16
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#define vp8_variance_var16x16 vp8_variance16x16_armv6
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#endif /* !CONFIG_RUNTIME_CPU_DETECT */
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#endif /* HAVE_ARMV6 */
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2010-05-18 17:58:33 +02:00
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#if HAVE_ARMV7
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extern prototype_sad(vp8_sad4x4_neon);
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extern prototype_sad(vp8_sad8x8_neon);
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extern prototype_sad(vp8_sad8x16_neon);
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extern prototype_sad(vp8_sad16x8_neon);
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extern prototype_sad(vp8_sad16x16_neon);
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//extern prototype_variance(vp8_variance4x4_c);
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extern prototype_variance(vp8_variance8x8_neon);
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extern prototype_variance(vp8_variance8x16_neon);
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extern prototype_variance(vp8_variance16x8_neon);
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extern prototype_variance(vp8_variance16x16_neon);
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//extern prototype_subpixvariance(vp8_sub_pixel_variance4x4_c);
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extern prototype_subpixvariance(vp8_sub_pixel_variance8x8_neon);
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//extern prototype_subpixvariance(vp8_sub_pixel_variance8x16_c);
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//extern prototype_subpixvariance(vp8_sub_pixel_variance16x8_c);
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extern prototype_subpixvariance(vp8_sub_pixel_variance16x16_neon);
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2011-01-25 21:11:39 +01:00
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extern prototype_subpixvariance(vp8_sub_pixel_variance16x16_neon_func);
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2010-10-26 21:34:16 +02:00
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extern prototype_variance(vp8_variance_halfpixvar16x16_h_neon);
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extern prototype_variance(vp8_variance_halfpixvar16x16_v_neon);
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extern prototype_variance(vp8_variance_halfpixvar16x16_hv_neon);
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2010-05-18 17:58:33 +02:00
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//extern prototype_getmbss(vp8_get_mb_ss_c);
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extern prototype_variance(vp8_mse16x16_neon);
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extern prototype_sad(vp8_get16x16pred_error_neon);
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//extern prototype_variance2(vp8_get8x8var_c);
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//extern prototype_variance2(vp8_get16x16var_c);
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extern prototype_sad(vp8_get4x4sse_cs_neon);
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Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
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#if !CONFIG_RUNTIME_CPU_DETECT
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2010-05-18 17:58:33 +02:00
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#undef vp8_variance_sad4x4
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#define vp8_variance_sad4x4 vp8_sad4x4_neon
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#undef vp8_variance_sad8x8
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#define vp8_variance_sad8x8 vp8_sad8x8_neon
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#undef vp8_variance_sad8x16
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#define vp8_variance_sad8x16 vp8_sad8x16_neon
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#undef vp8_variance_sad16x8
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#define vp8_variance_sad16x8 vp8_sad16x8_neon
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#undef vp8_variance_sad16x16
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#define vp8_variance_sad16x16 vp8_sad16x16_neon
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//#undef vp8_variance_var4x4
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//#define vp8_variance_var4x4 vp8_variance4x4_c
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#undef vp8_variance_var8x8
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#define vp8_variance_var8x8 vp8_variance8x8_neon
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#undef vp8_variance_var8x16
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#define vp8_variance_var8x16 vp8_variance8x16_neon
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#undef vp8_variance_var16x8
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#define vp8_variance_var16x8 vp8_variance16x8_neon
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#undef vp8_variance_var16x16
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#define vp8_variance_var16x16 vp8_variance16x16_neon
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//#undef vp8_variance_subpixvar4x4
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//#define vp8_variance_subpixvar4x4 vp8_sub_pixel_variance4x4_c
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#undef vp8_variance_subpixvar8x8
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#define vp8_variance_subpixvar8x8 vp8_sub_pixel_variance8x8_neon
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//#undef vp8_variance_subpixvar8x16
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//#define vp8_variance_subpixvar8x16 vp8_sub_pixel_variance8x16_c
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//#undef vp8_variance_subpixvar16x8
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//#define vp8_variance_subpixvar16x8 vp8_sub_pixel_variance16x8_c
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#undef vp8_variance_subpixvar16x16
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#define vp8_variance_subpixvar16x16 vp8_sub_pixel_variance16x16_neon
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2010-10-26 21:34:16 +02:00
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#undef vp8_variance_halfpixvar16x16_h
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#define vp8_variance_halfpixvar16x16_h vp8_variance_halfpixvar16x16_h_neon
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#undef vp8_variance_halfpixvar16x16_v
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#define vp8_variance_halfpixvar16x16_v vp8_variance_halfpixvar16x16_v_neon
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#undef vp8_variance_halfpixvar16x16_hv
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#define vp8_variance_halfpixvar16x16_hv vp8_variance_halfpixvar16x16_hv_neon
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2010-05-18 17:58:33 +02:00
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//#undef vp8_variance_getmbss
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//#define vp8_variance_getmbss vp8_get_mb_ss_c
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#undef vp8_variance_mse16x16
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#define vp8_variance_mse16x16 vp8_mse16x16_neon
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#undef vp8_variance_get16x16prederror
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#define vp8_variance_get16x16prederror vp8_get16x16pred_error_neon
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//#undef vp8_variance_get8x8var
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//#define vp8_variance_get8x8var vp8_get8x8var_c
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//#undef vp8_variance_get16x16var
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//#define vp8_variance_get16x16var vp8_get16x16var_c
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#undef vp8_variance_get4x4sse_cs
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#define vp8_variance_get4x4sse_cs vp8_get4x4sse_cs_neon
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Add runtime CPU detection support for ARM.
The primary goal is to allow a binary to be built which supports
NEON, but can fall back to non-NEON routines, since some Android
devices do not have NEON, even if they are otherwise ARMv7 (e.g.,
Tegra).
The configure-generated flags HAVE_ARMV7, etc., are used to decide
which versions of each function to build, and when
CONFIG_RUNTIME_CPU_DETECT is enabled, the correct version is chosen
at run time.
In order for this to work, the CFLAGS must be set to something
appropriate (e.g., without -mfpu=neon for ARMv7, and with
appropriate -march and -mcpu for even earlier configurations), or
the native C code will not be able to run.
The ASFLAGS must remain set for the most advanced instruction set
required at build time, since the ARM assembler will refuse to emit
them otherwise.
I have not attempted to make any changes to configure to do this
automatically.
Doing so will probably require the addition of new configure options.
Many of the hooks for RTCD on ARM were already there, but a lot of
the code had bit-rotted, and a good deal of the ARM-specific code
is not integrated into the RTCD structs at all.
I did not try to resolve the latter, merely to add the minimal amount
of protection around them to allow RTCD to work.
Those functions that were called based on an ifdef at the calling
site were expanded to check the RTCD flags at that site, but they
should be added to an RTCD struct somewhere in the future.
The functions invoked with global function pointers still are, but
these should be moved into an RTCD struct for thread safety (I
believe every platform currently supported has atomic pointer
stores, but this is not guaranteed).
The encoder's boolhuff functions did not even have _c and armv7
suffixes, and the correct version was resolved at link time.
The token packing functions did have appropriate suffixes, but the
version was selected with a define, with no associated RTCD struct.
However, for both of these, the only armv7 instruction they actually
used was rbit, and this was completely superfluous, so I reworked
them to avoid it.
The only non-ARMv4 instruction remaining in them is clz, which is
ARMv5 (not even ARMv5TE is required).
Considering that there are no ARM-specific configs which are not at
least ARMv5TE, I did not try to detect these at runtime, and simply
enable them for ARMv5 and above.
Finally, the NEON register saving code was completely non-reentrant,
since it saved the registers to a global, static variable.
I moved the storage for this onto the stack.
A single binary built with this code was tested on an ARM11 (ARMv6)
and a Cortex A8 (ARMv7 w/NEON), for both the encoder and decoder,
and produced identical output, while using the correct accelerated
functions on each.
I did not test on any earlier processors.
Change-Id: I45cbd63a614f4554c3b325c45d46c0806f009eaa
2010-10-21 00:39:11 +02:00
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#endif
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2010-05-18 17:58:33 +02:00
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#endif
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#endif
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