2015-05-04 13:45:55 +05:30
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/*
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* Copyright (c) 2015 The WebM project authors. All Rights Reserved.
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*
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* Use of this source code is governed by a BSD-style license
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* that can be found in the LICENSE file in the root of the source
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* tree. An additional intellectual property rights grant can be found
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* in the file PATENTS. All contributing project authors may
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* be found in the AUTHORS file in the root of the source tree.
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*/
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2015-06-02 12:16:28 +05:30
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#include <assert.h>
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2015-07-31 10:53:25 -07:00
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#include "vp9/common/vp9_enums.h"
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2015-07-31 11:15:55 -07:00
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#include "vpx_dsp/mips/inv_txfm_msa.h"
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2015-05-04 13:45:55 +05:30
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2015-06-01 09:19:01 +05:30
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void vp9_iht16x16_256_add_msa(const int16_t *input, uint8_t *dst,
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int32_t dst_stride, int32_t tx_type) {
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2015-05-04 13:45:55 +05:30
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int32_t i;
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DECLARE_ALIGNED(32, int16_t, out[16 * 16]);
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int16_t *out_ptr = &out[0];
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switch (tx_type) {
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case DCT_DCT:
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/* transform rows */
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for (i = 0; i < 2; ++i) {
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/* process 16 * 8 block */
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2015-08-03 14:51:10 -07:00
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vpx_idct16_1d_rows_msa((input + (i << 7)), (out_ptr + (i << 7)));
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2015-05-04 13:45:55 +05:30
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}
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/* transform columns */
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for (i = 0; i < 2; ++i) {
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/* process 8 * 16 block */
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2015-08-03 14:51:10 -07:00
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vpx_idct16_1d_columns_addblk_msa((out_ptr + (i << 3)), (dst + (i << 3)),
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2015-06-01 09:19:01 +05:30
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dst_stride);
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2015-05-04 13:45:55 +05:30
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}
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break;
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case ADST_DCT:
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/* transform rows */
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for (i = 0; i < 2; ++i) {
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/* process 16 * 8 block */
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2015-08-03 14:51:10 -07:00
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vpx_idct16_1d_rows_msa((input + (i << 7)), (out_ptr + (i << 7)));
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2015-05-04 13:45:55 +05:30
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}
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/* transform columns */
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for (i = 0; i < 2; ++i) {
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2015-08-03 14:51:10 -07:00
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vpx_iadst16_1d_columns_addblk_msa((out_ptr + (i << 3)),
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2015-06-01 09:19:01 +05:30
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(dst + (i << 3)), dst_stride);
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2015-05-04 13:45:55 +05:30
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}
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break;
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case DCT_ADST:
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/* transform rows */
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for (i = 0; i < 2; ++i) {
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/* process 16 * 8 block */
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2015-08-03 14:51:10 -07:00
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vpx_iadst16_1d_rows_msa((input + (i << 7)), (out_ptr + (i << 7)));
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2015-05-04 13:45:55 +05:30
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}
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/* transform columns */
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for (i = 0; i < 2; ++i) {
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/* process 8 * 16 block */
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2015-08-03 14:51:10 -07:00
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vpx_idct16_1d_columns_addblk_msa((out_ptr + (i << 3)), (dst + (i << 3)),
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2015-06-01 09:19:01 +05:30
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dst_stride);
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2015-05-04 13:45:55 +05:30
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}
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break;
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case ADST_ADST:
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/* transform rows */
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for (i = 0; i < 2; ++i) {
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/* process 16 * 8 block */
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2015-08-03 14:51:10 -07:00
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vpx_iadst16_1d_rows_msa((input + (i << 7)), (out_ptr + (i << 7)));
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2015-05-04 13:45:55 +05:30
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}
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/* transform columns */
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for (i = 0; i < 2; ++i) {
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2015-08-03 14:51:10 -07:00
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vpx_iadst16_1d_columns_addblk_msa((out_ptr + (i << 3)),
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2015-06-01 09:19:01 +05:30
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(dst + (i << 3)), dst_stride);
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2015-05-04 13:45:55 +05:30
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}
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break;
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2016-07-26 16:52:55 -07:00
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default: assert(0); break;
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2015-05-04 13:45:55 +05:30
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}
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}
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