2010-05-18 17:58:33 +02:00
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;
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2010-09-09 14:16:39 +02:00
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; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
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2010-05-18 17:58:33 +02:00
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;
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2010-06-18 18:39:21 +02:00
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; Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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; in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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; be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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;
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EXPORT |vp8_mse16x16_neon|
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EXPORT |vp8_get4x4sse_cs_neon|
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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;============================
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; r0 unsigned char *src_ptr
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; r1 int source_stride
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; r2 unsigned char *ref_ptr
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; r3 int recon_stride
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; stack unsigned int *sse
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;note: in this function, sum is never used. So, we can remove this part of calculation
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2012-10-31 22:40:53 +01:00
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;from vp9_variance().
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2010-05-18 17:58:33 +02:00
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|vp8_mse16x16_neon| PROC
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vmov.i8 q7, #0 ;q7, q8, q9, q10 - sse
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vmov.i8 q8, #0
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vmov.i8 q9, #0
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vmov.i8 q10, #0
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mov r12, #8
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mse16x16_neon_loop
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vld1.8 {q0}, [r0], r1 ;Load up source and reference
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vld1.8 {q2}, [r2], r3
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vld1.8 {q1}, [r0], r1
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vld1.8 {q3}, [r2], r3
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vsubl.u8 q11, d0, d4
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vsubl.u8 q12, d1, d5
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vsubl.u8 q13, d2, d6
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vsubl.u8 q14, d3, d7
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vmlal.s16 q7, d22, d22
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vmlal.s16 q8, d23, d23
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subs r12, r12, #1
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vmlal.s16 q9, d24, d24
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vmlal.s16 q10, d25, d25
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vmlal.s16 q7, d26, d26
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vmlal.s16 q8, d27, d27
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vmlal.s16 q9, d28, d28
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vmlal.s16 q10, d29, d29
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bne mse16x16_neon_loop
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vadd.u32 q7, q7, q8
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vadd.u32 q9, q9, q10
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ldr r12, [sp] ;load *sse from stack
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vadd.u32 q10, q7, q9
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vpaddl.u32 q1, q10
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vadd.u64 d0, d2, d3
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vst1.32 {d0[0]}, [r12]
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vmov.32 r0, d0[0]
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bx lr
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ENDP
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;=============================
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; r0 unsigned char *src_ptr,
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; r1 int source_stride,
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; r2 unsigned char *ref_ptr,
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; r3 int recon_stride
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|vp8_get4x4sse_cs_neon| PROC
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vld1.8 {d0}, [r0], r1 ;Load up source and reference
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vld1.8 {d4}, [r2], r3
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vld1.8 {d1}, [r0], r1
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vld1.8 {d5}, [r2], r3
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vld1.8 {d2}, [r0], r1
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vld1.8 {d6}, [r2], r3
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vld1.8 {d3}, [r0], r1
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vld1.8 {d7}, [r2], r3
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vsubl.u8 q11, d0, d4
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vsubl.u8 q12, d1, d5
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vsubl.u8 q13, d2, d6
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vsubl.u8 q14, d3, d7
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vmull.s16 q7, d22, d22
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vmull.s16 q8, d24, d24
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vmull.s16 q9, d26, d26
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vmull.s16 q10, d28, d28
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vadd.u32 q7, q7, q8
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vadd.u32 q9, q9, q10
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vadd.u32 q9, q7, q9
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vpaddl.u32 q1, q9
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vadd.u64 d0, d2, d3
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vmov.32 r0, d0[0]
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bx lr
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ENDP
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END
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