2013-08-14 17:18:08 +02:00
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;
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; Copyright (c) 2013 The WebM project authors. All Rights Reserved.
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;
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; Use of this source code is governed by a BSD-style license
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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; in the file PATENTS. All contributing project authors may
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; be found in the AUTHORS file in the root of the source tree.
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;
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2015-07-22 19:40:42 +02:00
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EXPORT |vpx_convolve_avg_neon|
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2013-08-14 17:18:08 +02:00
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ARM
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REQUIRE8
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PRESERVE8
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AREA ||.text||, CODE, READONLY, ALIGN=2
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2015-07-22 19:40:42 +02:00
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|vpx_convolve_avg_neon| PROC
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2013-08-14 17:18:08 +02:00
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push {r4-r6, lr}
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ldrd r4, r5, [sp, #32]
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mov r6, r2
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cmp r4, #32
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bgt avg64
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beq avg32
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cmp r4, #8
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bgt avg16
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beq avg8
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b avg4
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avg64
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sub lr, r1, #32
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sub r4, r3, #32
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avg64_h
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pld [r0, r1, lsl #1]
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vld1.8 {q0-q1}, [r0]!
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vld1.8 {q2-q3}, [r0], lr
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pld [r2, r3]
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vld1.8 {q8-q9}, [r6@128]!
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vld1.8 {q10-q11}, [r6@128], r4
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vrhadd.u8 q0, q0, q8
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vrhadd.u8 q1, q1, q9
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vrhadd.u8 q2, q2, q10
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vrhadd.u8 q3, q3, q11
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vst1.8 {q0-q1}, [r2@128]!
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vst1.8 {q2-q3}, [r2@128], r4
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subs r5, r5, #1
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bgt avg64_h
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pop {r4-r6, pc}
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avg32
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vld1.8 {q0-q1}, [r0], r1
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vld1.8 {q2-q3}, [r0], r1
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vld1.8 {q8-q9}, [r6@128], r3
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vld1.8 {q10-q11}, [r6@128], r3
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pld [r0]
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vrhadd.u8 q0, q0, q8
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pld [r0, r1]
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vrhadd.u8 q1, q1, q9
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pld [r6]
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vrhadd.u8 q2, q2, q10
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pld [r6, r3]
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vrhadd.u8 q3, q3, q11
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vst1.8 {q0-q1}, [r2@128], r3
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vst1.8 {q2-q3}, [r2@128], r3
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subs r5, r5, #2
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bgt avg32
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pop {r4-r6, pc}
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avg16
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vld1.8 {q0}, [r0], r1
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vld1.8 {q1}, [r0], r1
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vld1.8 {q2}, [r6@128], r3
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vld1.8 {q3}, [r6@128], r3
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pld [r0]
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pld [r0, r1]
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vrhadd.u8 q0, q0, q2
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pld [r6]
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pld [r6, r3]
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vrhadd.u8 q1, q1, q3
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vst1.8 {q0}, [r2@128], r3
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vst1.8 {q1}, [r2@128], r3
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subs r5, r5, #2
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bgt avg16
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pop {r4-r6, pc}
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avg8
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vld1.8 {d0}, [r0], r1
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vld1.8 {d1}, [r0], r1
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vld1.8 {d2}, [r6@64], r3
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vld1.8 {d3}, [r6@64], r3
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pld [r0]
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pld [r0, r1]
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vrhadd.u8 q0, q0, q1
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pld [r6]
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pld [r6, r3]
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vst1.8 {d0}, [r2@64], r3
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vst1.8 {d1}, [r2@64], r3
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subs r5, r5, #2
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bgt avg8
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pop {r4-r6, pc}
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avg4
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vld1.32 {d0[0]}, [r0], r1
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vld1.32 {d0[1]}, [r0], r1
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vld1.32 {d2[0]}, [r6@32], r3
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vld1.32 {d2[1]}, [r6@32], r3
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vrhadd.u8 d0, d0, d2
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vst1.32 {d0[0]}, [r2@32], r3
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vst1.32 {d0[1]}, [r2@32], r3
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subs r5, r5, #2
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bgt avg4
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pop {r4-r6, pc}
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ENDP
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END
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