2010-05-18 17:58:33 +02:00
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;
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; Copyright (c) 2010 The VP8 project authors. All Rights Reserved.
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;
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2010-06-18 18:39:21 +02:00
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; Use of this source code is governed by a BSD-style license
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2010-06-04 22:19:40 +02:00
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; that can be found in the LICENSE file in the root of the source
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; tree. An additional intellectual property rights grant can be found
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2010-06-18 18:39:21 +02:00
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; in the file PATENTS. All contributing project authors may
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2010-06-04 22:19:40 +02:00
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; be found in the AUTHORS file in the root of the source tree.
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2010-05-18 17:58:33 +02:00
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;
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%include "vpx_ports/x86_abi_support.asm"
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;void vp8_short_walsh4x4_sse2(short *input, short *output, int pitch)
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global sym(vp8_short_walsh4x4_sse2)
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sym(vp8_short_walsh4x4_sse2):
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push rbp
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mov rbp, rsp
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SHADOW_ARGS_TO_STACK 3
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push rsi
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push rdi
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; end prolog
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mov rsi, arg(0)
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mov rdi, arg(1)
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movdqu xmm4, [rsi + 0] ;ip[4] ip[0]
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movdqu xmm0, [rsi + 16] ;ip[12] ip[8]
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pxor xmm7, xmm7
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;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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; 13 12 11 10 03 02 01 00
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;
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; 33 32 31 30 23 22 21 20
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;
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movdqa xmm3, xmm4 ; 13 12 11 10 03 02 01 00
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punpcklwd xmm4, xmm0 ; 23 03 22 02 21 01 20 00
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punpckhwd xmm3, xmm0 ; 33 13 32 12 31 11 30 10
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movdqa xmm1, xmm4 ; 23 03 22 02 21 01 20 00
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punpcklwd xmm4, xmm3 ; 31 21 11 01 30 20 10 00
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punpckhwd xmm1, xmm3 ; 33 23 13 03 32 22 12 02
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;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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pshufd xmm2, xmm1, 4eh ;ip[8] ip[12]
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movdqa xmm3, xmm4 ;ip[4] ip[0]
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paddw xmm4, xmm2 ;ip[4]+ip[8] ip[0]+ip[12] aka b1 a1
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psubw xmm3, xmm2 ;ip[4]-ip[8] ip[0]-ip[12] aka c1 d1
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movdqa xmm5, xmm4
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punpcklqdq xmm4, xmm3 ;d1 a1
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punpckhqdq xmm5, xmm3 ;c1 b1
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movdqa xmm1, xmm5 ;c1 b1
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paddw xmm5, xmm4 ;dl+cl a1+b1 aka op[4] op[0]
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psubw xmm4, xmm1 ;d1-c1 a1-b1 aka op[12] op[8]
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;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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; 13 12 11 10 03 02 01 00
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;
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; 33 32 31 30 23 22 21 20
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;
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movdqa xmm0, xmm5 ; 13 12 11 10 03 02 01 00
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punpcklwd xmm5, xmm4 ; 23 03 22 02 21 01 20 00
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punpckhwd xmm0, xmm4 ; 33 13 32 12 31 11 30 10
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movdqa xmm1, xmm5 ; 23 03 22 02 21 01 20 00
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punpcklwd xmm5, xmm0 ; 31 21 11 01 30 20 10 00
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punpckhwd xmm1, xmm0 ; 33 23 13 03 32 22 12 02
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;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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pshufd xmm2, xmm1, 4eh ;ip[8] ip[12]
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movdqa xmm3, xmm5 ;ip[4] ip[0]
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paddw xmm5, xmm2 ;ip[4]+ip[8] ip[0]+ip[12] aka b1 a1
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psubw xmm3, xmm2 ;ip[4]-ip[8] ip[0]-ip[12] aka c1 d1
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movdqa xmm6, xmm5
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punpcklqdq xmm5, xmm3 ;d1 a1
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punpckhqdq xmm6, xmm3 ;c1 b1
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movdqa xmm1, xmm6 ;c1 b1
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paddw xmm6, xmm5 ;dl+cl a1+b1 aka op[4] op[0]
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psubw xmm5, xmm1 ;d1-c1 a1-b1 aka op[12] op[8]
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movdqa xmm0, xmm6 ;aka b2 a2
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movdqa xmm1, xmm5 ;aka d2 c2
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pcmpgtw xmm0, xmm7
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pcmpgtw xmm1, xmm7
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psrlw xmm0, 15
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psrlw xmm1, 15
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paddw xmm6, xmm0
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paddw xmm5, xmm1
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psraw xmm6, 1
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psraw xmm5, 1
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; a2 = a1 + b1;
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; b2 = c1 + d1;
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; c2 = a1 - b1;
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; d2 = d1 - c1;
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; a2 += (a2>0);
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; b2 += (b2>0);
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; c2 += (c2>0);
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; d2 += (d2>0);
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; op[0] = (a2)>>1;
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; op[4] = (b2)>>1;
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; op[8] = (c2)>>1;
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; op[12]= (d2)>>1;
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movdqu [rdi + 0], xmm6
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movdqu [rdi + 16], xmm5
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; begin epilog
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pop rdi
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pop rsi
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UNSHADOW_ARGS
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pop rbp
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ret
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