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vpx/vp8/common/arm/neon/sixtappredict8x4_neon.asm

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Initial WebM release
2010-05-18 17:58:33 +02:00
;
Use WebM in copyright notice for consistency Changes 'The VP8 project' to 'The WebM project', for consistency with other webmproject.org repositories. Fixes issue #97. Change-Id: I37c13ed5fbdb9d334ceef71c6350e9febed9bbba
2010-09-09 14:16:39 +02:00
; Copyright (c) 2010 The WebM project authors. All Rights Reserved.
Initial WebM release
2010-05-18 17:58:33 +02:00
;
cosmetics: trim trailing whitespace When the license headers were updated, they accidentally contained trailing whitespace, so unfortunately we have to touch all the files again. Change-Id: I236c05fade06589e417179c0444cb39b09e4200d
2010-06-18 18:39:21 +02:00
; Use of this source code is governed by a BSD-style license
LICENSE: update with latest text Change-Id: Ieebea089095d9073b3a94932791099f614ce120c
2010-06-04 22:19:40 +02:00
; that can be found in the LICENSE file in the root of the source
; tree. An additional intellectual property rights grant can be found
cosmetics: trim trailing whitespace When the license headers were updated, they accidentally contained trailing whitespace, so unfortunately we have to touch all the files again. Change-Id: I236c05fade06589e417179c0444cb39b09e4200d
2010-06-18 18:39:21 +02:00
; in the file PATENTS. All contributing project authors may
LICENSE: update with latest text Change-Id: Ieebea089095d9073b3a94932791099f614ce120c
2010-06-04 22:19:40 +02:00
; be found in the AUTHORS file in the root of the source tree.
Initial WebM release
2010-05-18 17:58:33 +02:00
;
EXPORT |vp8_sixtap_predict8x4_neon|
ARM
REQUIRE8
PRESERVE8
AREA ||.text||, CODE, READONLY, ALIGN=2
Avoid text relocations in ARM vp8 decoder The current code stores pointers to coefficient tables and loads them to access the tables contents. As these pointers are stored in the code sections, it means we end up with text relocations. eu-findtextrel will thus complain about code not compiled with -fpic/-fPIC. Since the pointers are stored in the code sections, we can actually cheat and let the assembler generate relative addressing when accessing the coefficient tables, and just load their location with adr. Change-Id: Ib74ae2d3f2bab80b29991355f2dbe6955f38f6ae
2011-06-17 02:33:52 +02:00
filter8_coeff
DCD 0, 0, 128, 0, 0, 0, 0, 0
DCD 0, -6, 123, 12, -1, 0, 0, 0
DCD 2, -11, 108, 36, -8, 1, 0, 0
DCD 0, -9, 93, 50, -6, 0, 0, 0
DCD 3, -16, 77, 77, -16, 3, 0, 0
DCD 0, -6, 50, 93, -9, 0, 0, 0
DCD 1, -8, 36, 108, -11, 2, 0, 0
DCD 0, -1, 12, 123, -6, 0, 0, 0
Initial WebM release
2010-05-18 17:58:33 +02:00
; r0 unsigned char *src_ptr,
; r1 int src_pixels_per_line,
; r2 int xoffset,
; r3 int yoffset,
; r4 unsigned char *dst_ptr,
; stack(r5) int dst_pitch
|vp8_sixtap_predict8x4_neon| PROC
push {r4-r5, lr}
Save NEON registers in VP8 NEON functions The recent compiler can generate optimized code that uses NEON registers for various operations besides floating-point operations. Therefore, only saving callee-saved registers d8 - d15 at the beginning of the encoder/decoder is not enough anymore. This patch added register saving code in VP8 NEON functions that use those registers. Change-Id: Ie9e44f5188cf410990c8aaaac68faceee9dffd31
2014-04-28 23:42:23 +02:00
vpush {d8-d15}
Initial WebM release
2010-05-18 17:58:33 +02:00
Avoid text relocations in ARM vp8 decoder The current code stores pointers to coefficient tables and loads them to access the tables contents. As these pointers are stored in the code sections, it means we end up with text relocations. eu-findtextrel will thus complain about code not compiled with -fpic/-fPIC. Since the pointers are stored in the code sections, we can actually cheat and let the assembler generate relative addressing when accessing the coefficient tables, and just load their location with adr. Change-Id: Ib74ae2d3f2bab80b29991355f2dbe6955f38f6ae
2011-06-17 02:33:52 +02:00
adr r12, filter8_coeff
Save NEON registers in VP8 NEON functions The recent compiler can generate optimized code that uses NEON registers for various operations besides floating-point operations. Therefore, only saving callee-saved registers d8 - d15 at the beginning of the encoder/decoder is not enough anymore. This patch added register saving code in VP8 NEON functions that use those registers. Change-Id: Ie9e44f5188cf410990c8aaaac68faceee9dffd31
2014-04-28 23:42:23 +02:00
ldr r4, [sp, #76] ;load parameters from stack
ldr r5, [sp, #80] ;load parameters from stack
Initial WebM release
2010-05-18 17:58:33 +02:00
cmp r2, #0 ;skip first_pass filter if xoffset=0
beq secondpass_filter8x4_only
add r2, r12, r2, lsl #5 ;calculate filter location
cmp r3, #0 ;skip second_pass filter if yoffset=0
vld1.s32 {q14, q15}, [r2] ;load first_pass filter
beq firstpass_filter8x4_only
sub sp, sp, #32 ;reserve space on stack for temporary storage
vabs.s32 q12, q14
vabs.s32 q13, q15
sub r0, r0, #2 ;move srcptr back to (line-2) and (column-2)
mov lr, sp
sub r0, r0, r1, lsl #1
vdup.8 d0, d24[0] ;first_pass filter (d0-d5)
vdup.8 d1, d24[4]
vdup.8 d2, d25[0]
;First pass: output_height lines x output_width columns (9x8)
vld1.u8 {q3}, [r0], r1 ;load src data
vdup.8 d3, d25[4]
vld1.u8 {q4}, [r0], r1
vdup.8 d4, d26[0]
vld1.u8 {q5}, [r0], r1
vdup.8 d5, d26[4]
vld1.u8 {q6}, [r0], r1
pld [r0]
pld [r0, r1]
pld [r0, r1, lsl #1]
vmull.u8 q7, d6, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q8, d8, d0
vmull.u8 q9, d10, d0
vmull.u8 q10, d12, d0
vext.8 d28, d6, d7, #1 ;construct src_ptr[-1]
vext.8 d29, d8, d9, #1
vext.8 d30, d10, d11, #1
vext.8 d31, d12, d13, #1
vmlsl.u8 q7, d28, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q8, d29, d1
vmlsl.u8 q9, d30, d1
vmlsl.u8 q10, d31, d1
vext.8 d28, d6, d7, #4 ;construct src_ptr[2]
vext.8 d29, d8, d9, #4
vext.8 d30, d10, d11, #4
vext.8 d31, d12, d13, #4
vmlsl.u8 q7, d28, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q8, d29, d4
vmlsl.u8 q9, d30, d4
vmlsl.u8 q10, d31, d4
vext.8 d28, d6, d7, #2 ;construct src_ptr[0]
vext.8 d29, d8, d9, #2
vext.8 d30, d10, d11, #2
vext.8 d31, d12, d13, #2
vmlal.u8 q7, d28, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q8, d29, d2
vmlal.u8 q9, d30, d2
vmlal.u8 q10, d31, d2
vext.8 d28, d6, d7, #5 ;construct src_ptr[3]
vext.8 d29, d8, d9, #5
vext.8 d30, d10, d11, #5
vext.8 d31, d12, d13, #5
vmlal.u8 q7, d28, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q8, d29, d5
vmlal.u8 q9, d30, d5
vmlal.u8 q10, d31, d5
vext.8 d28, d6, d7, #3 ;construct src_ptr[1]
vext.8 d29, d8, d9, #3
vext.8 d30, d10, d11, #3
vext.8 d31, d12, d13, #3
vmull.u8 q3, d28, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q4, d29, d3
vmull.u8 q5, d30, d3
vmull.u8 q6, d31, d3
vqadd.s16 q7, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q8, q4
vqadd.s16 q9, q5
vqadd.s16 q10, q6
vld1.u8 {q3}, [r0], r1 ;load src data
vqrshrun.s16 d22, q7, #7 ;shift/round/saturate to u8
vqrshrun.s16 d23, q8, #7
vqrshrun.s16 d24, q9, #7
vqrshrun.s16 d25, q10, #7
vld1.u8 {q4}, [r0], r1
vst1.u8 {d22}, [lr]! ;store result
vld1.u8 {q5}, [r0], r1
vst1.u8 {d23}, [lr]!
vld1.u8 {q6}, [r0], r1
vst1.u8 {d24}, [lr]!
vld1.u8 {q7}, [r0], r1
vst1.u8 {d25}, [lr]!
;first_pass filtering on the rest 5-line data
vmull.u8 q8, d6, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q9, d8, d0
vmull.u8 q10, d10, d0
vmull.u8 q11, d12, d0
vmull.u8 q12, d14, d0
vext.8 d27, d6, d7, #1 ;construct src_ptr[-1]
vext.8 d28, d8, d9, #1
vext.8 d29, d10, d11, #1
vext.8 d30, d12, d13, #1
vext.8 d31, d14, d15, #1
vmlsl.u8 q8, d27, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q9, d28, d1
vmlsl.u8 q10, d29, d1
vmlsl.u8 q11, d30, d1
vmlsl.u8 q12, d31, d1
vext.8 d27, d6, d7, #4 ;construct src_ptr[2]
vext.8 d28, d8, d9, #4
vext.8 d29, d10, d11, #4
vext.8 d30, d12, d13, #4
vext.8 d31, d14, d15, #4
vmlsl.u8 q8, d27, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q9, d28, d4
vmlsl.u8 q10, d29, d4
vmlsl.u8 q11, d30, d4
vmlsl.u8 q12, d31, d4
vext.8 d27, d6, d7, #2 ;construct src_ptr[0]
vext.8 d28, d8, d9, #2
vext.8 d29, d10, d11, #2
vext.8 d30, d12, d13, #2
vext.8 d31, d14, d15, #2
vmlal.u8 q8, d27, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q9, d28, d2
vmlal.u8 q10, d29, d2
vmlal.u8 q11, d30, d2
vmlal.u8 q12, d31, d2
vext.8 d27, d6, d7, #5 ;construct src_ptr[3]
vext.8 d28, d8, d9, #5
vext.8 d29, d10, d11, #5
vext.8 d30, d12, d13, #5
vext.8 d31, d14, d15, #5
vmlal.u8 q8, d27, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q9, d28, d5
vmlal.u8 q10, d29, d5
vmlal.u8 q11, d30, d5
vmlal.u8 q12, d31, d5
vext.8 d27, d6, d7, #3 ;construct src_ptr[1]
vext.8 d28, d8, d9, #3
vext.8 d29, d10, d11, #3
vext.8 d30, d12, d13, #3
vext.8 d31, d14, d15, #3
vmull.u8 q3, d27, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q4, d28, d3
vmull.u8 q5, d29, d3
vmull.u8 q6, d30, d3
vmull.u8 q7, d31, d3
vqadd.s16 q8, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q9, q4
vqadd.s16 q10, q5
vqadd.s16 q11, q6
vqadd.s16 q12, q7
vqrshrun.s16 d26, q8, #7 ;shift/round/saturate to u8
vqrshrun.s16 d27, q9, #7
vqrshrun.s16 d28, q10, #7
vqrshrun.s16 d29, q11, #7 ;load intermediate data from stack
vqrshrun.s16 d30, q12, #7
;Second pass: 8x4
;secondpass_filter
add r3, r12, r3, lsl #5
sub lr, lr, #32
vld1.s32 {q5, q6}, [r3] ;load second_pass filter
vld1.u8 {q11}, [lr]!
vabs.s32 q7, q5
vabs.s32 q8, q6
vld1.u8 {q12}, [lr]!
vdup.8 d0, d14[0] ;second_pass filter parameters (d0-d5)
vdup.8 d1, d14[4]
vdup.8 d2, d15[0]
vdup.8 d3, d15[4]
vdup.8 d4, d16[0]
vdup.8 d5, d16[4]
vmull.u8 q3, d22, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q4, d23, d0
vmull.u8 q5, d24, d0
vmull.u8 q6, d25, d0
vmlsl.u8 q3, d23, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q4, d24, d1
vmlsl.u8 q5, d25, d1
vmlsl.u8 q6, d26, d1
vmlsl.u8 q3, d26, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q4, d27, d4
vmlsl.u8 q5, d28, d4
vmlsl.u8 q6, d29, d4
vmlal.u8 q3, d24, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q4, d25, d2
vmlal.u8 q5, d26, d2
vmlal.u8 q6, d27, d2
vmlal.u8 q3, d27, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q4, d28, d5
vmlal.u8 q5, d29, d5
vmlal.u8 q6, d30, d5
vmull.u8 q7, d25, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q8, d26, d3
vmull.u8 q9, d27, d3
vmull.u8 q10, d28, d3
vqadd.s16 q7, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q8, q4
vqadd.s16 q9, q5
vqadd.s16 q10, q6
vqrshrun.s16 d6, q7, #7 ;shift/round/saturate to u8
vqrshrun.s16 d7, q8, #7
vqrshrun.s16 d8, q9, #7
vqrshrun.s16 d9, q10, #7
vst1.u8 {d6}, [r4], r5 ;store result
vst1.u8 {d7}, [r4], r5
vst1.u8 {d8}, [r4], r5
vst1.u8 {d9}, [r4], r5
add sp, sp, #32
Save NEON registers in VP8 NEON functions The recent compiler can generate optimized code that uses NEON registers for various operations besides floating-point operations. Therefore, only saving callee-saved registers d8 - d15 at the beginning of the encoder/decoder is not enough anymore. This patch added register saving code in VP8 NEON functions that use those registers. Change-Id: Ie9e44f5188cf410990c8aaaac68faceee9dffd31
2014-04-28 23:42:23 +02:00
vpop {d8-d15}
Initial WebM release
2010-05-18 17:58:33 +02:00
pop {r4-r5,pc}
;--------------------
firstpass_filter8x4_only
vabs.s32 q12, q14
vabs.s32 q13, q15
sub r0, r0, #2 ;move srcptr back to (line-2) and (column-2)
vld1.u8 {q3}, [r0], r1 ;load src data
vdup.8 d0, d24[0] ;first_pass filter (d0-d5)
vld1.u8 {q4}, [r0], r1
vdup.8 d1, d24[4]
vld1.u8 {q5}, [r0], r1
vdup.8 d2, d25[0]
vld1.u8 {q6}, [r0], r1
vdup.8 d3, d25[4]
vdup.8 d4, d26[0]
vdup.8 d5, d26[4]
;First pass: output_height lines x output_width columns (4x8)
pld [r0]
pld [r0, r1]
pld [r0, r1, lsl #1]
vmull.u8 q7, d6, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q8, d8, d0
vmull.u8 q9, d10, d0
vmull.u8 q10, d12, d0
vext.8 d28, d6, d7, #1 ;construct src_ptr[-1]
vext.8 d29, d8, d9, #1
vext.8 d30, d10, d11, #1
vext.8 d31, d12, d13, #1
vmlsl.u8 q7, d28, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q8, d29, d1
vmlsl.u8 q9, d30, d1
vmlsl.u8 q10, d31, d1
vext.8 d28, d6, d7, #4 ;construct src_ptr[2]
vext.8 d29, d8, d9, #4
vext.8 d30, d10, d11, #4
vext.8 d31, d12, d13, #4
vmlsl.u8 q7, d28, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q8, d29, d4
vmlsl.u8 q9, d30, d4
vmlsl.u8 q10, d31, d4
vext.8 d28, d6, d7, #2 ;construct src_ptr[0]
vext.8 d29, d8, d9, #2
vext.8 d30, d10, d11, #2
vext.8 d31, d12, d13, #2
vmlal.u8 q7, d28, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q8, d29, d2
vmlal.u8 q9, d30, d2
vmlal.u8 q10, d31, d2
vext.8 d28, d6, d7, #5 ;construct src_ptr[3]
vext.8 d29, d8, d9, #5
vext.8 d30, d10, d11, #5
vext.8 d31, d12, d13, #5
vmlal.u8 q7, d28, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q8, d29, d5
vmlal.u8 q9, d30, d5
vmlal.u8 q10, d31, d5
vext.8 d28, d6, d7, #3 ;construct src_ptr[1]
vext.8 d29, d8, d9, #3
vext.8 d30, d10, d11, #3
vext.8 d31, d12, d13, #3
vmull.u8 q3, d28, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q4, d29, d3
vmull.u8 q5, d30, d3
vmull.u8 q6, d31, d3
vqadd.s16 q7, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q8, q4
vqadd.s16 q9, q5
vqadd.s16 q10, q6
vqrshrun.s16 d22, q7, #7 ;shift/round/saturate to u8
vqrshrun.s16 d23, q8, #7
vqrshrun.s16 d24, q9, #7
vqrshrun.s16 d25, q10, #7
vst1.u8 {d22}, [r4], r5 ;store result
vst1.u8 {d23}, [r4], r5
vst1.u8 {d24}, [r4], r5
vst1.u8 {d25}, [r4], r5
Save NEON registers in VP8 NEON functions The recent compiler can generate optimized code that uses NEON registers for various operations besides floating-point operations. Therefore, only saving callee-saved registers d8 - d15 at the beginning of the encoder/decoder is not enough anymore. This patch added register saving code in VP8 NEON functions that use those registers. Change-Id: Ie9e44f5188cf410990c8aaaac68faceee9dffd31
2014-04-28 23:42:23 +02:00
vpop {d8-d15}
Initial WebM release
2010-05-18 17:58:33 +02:00
pop {r4-r5,pc}
;---------------------
secondpass_filter8x4_only
;Second pass: 8x4
add r3, r12, r3, lsl #5
sub r0, r0, r1, lsl #1
vld1.s32 {q5, q6}, [r3] ;load second_pass filter
vabs.s32 q7, q5
vabs.s32 q8, q6
vld1.u8 {d22}, [r0], r1
vld1.u8 {d23}, [r0], r1
vld1.u8 {d24}, [r0], r1
vdup.8 d0, d14[0] ;second_pass filter parameters (d0-d5)
vld1.u8 {d25}, [r0], r1
vdup.8 d1, d14[4]
vld1.u8 {d26}, [r0], r1
vdup.8 d2, d15[0]
vld1.u8 {d27}, [r0], r1
vdup.8 d3, d15[4]
vld1.u8 {d28}, [r0], r1
vdup.8 d4, d16[0]
vld1.u8 {d29}, [r0], r1
vdup.8 d5, d16[4]
vld1.u8 {d30}, [r0], r1
vmull.u8 q3, d22, d0 ;(src_ptr[-2] * vp8_filter[0])
vmull.u8 q4, d23, d0
vmull.u8 q5, d24, d0
vmull.u8 q6, d25, d0
vmlsl.u8 q3, d23, d1 ;-(src_ptr[-1] * vp8_filter[1])
vmlsl.u8 q4, d24, d1
vmlsl.u8 q5, d25, d1
vmlsl.u8 q6, d26, d1
vmlsl.u8 q3, d26, d4 ;-(src_ptr[2] * vp8_filter[4])
vmlsl.u8 q4, d27, d4
vmlsl.u8 q5, d28, d4
vmlsl.u8 q6, d29, d4
vmlal.u8 q3, d24, d2 ;(src_ptr[0] * vp8_filter[2])
vmlal.u8 q4, d25, d2
vmlal.u8 q5, d26, d2
vmlal.u8 q6, d27, d2
vmlal.u8 q3, d27, d5 ;(src_ptr[3] * vp8_filter[5])
vmlal.u8 q4, d28, d5
vmlal.u8 q5, d29, d5
vmlal.u8 q6, d30, d5
vmull.u8 q7, d25, d3 ;(src_ptr[1] * vp8_filter[3])
vmull.u8 q8, d26, d3
vmull.u8 q9, d27, d3
vmull.u8 q10, d28, d3
vqadd.s16 q7, q3 ;sum of all (src_data*filter_parameters)
vqadd.s16 q8, q4
vqadd.s16 q9, q5
vqadd.s16 q10, q6
vqrshrun.s16 d6, q7, #7 ;shift/round/saturate to u8
vqrshrun.s16 d7, q8, #7
vqrshrun.s16 d8, q9, #7
vqrshrun.s16 d9, q10, #7
vst1.u8 {d6}, [r4], r5 ;store result
vst1.u8 {d7}, [r4], r5
vst1.u8 {d8}, [r4], r5
vst1.u8 {d9}, [r4], r5
Save NEON registers in VP8 NEON functions The recent compiler can generate optimized code that uses NEON registers for various operations besides floating-point operations. Therefore, only saving callee-saved registers d8 - d15 at the beginning of the encoder/decoder is not enough anymore. This patch added register saving code in VP8 NEON functions that use those registers. Change-Id: Ie9e44f5188cf410990c8aaaac68faceee9dffd31
2014-04-28 23:42:23 +02:00
vpop {d8-d15}
Initial WebM release
2010-05-18 17:58:33 +02:00
pop {r4-r5,pc}
ENDP
;-----------------
Adds "armvX-none-rvct" targets Adds following targets to configure script to support RVCT compilation without operating system support (for Profiler or bare metal images). - armv5te-none-rvct - armv6-none-rvct - armv7-none-rvct To strip OS specific parts from the code "os_support"-config was added to script and CONFIG_OS_SUPPORT flag is used in the code to exclude OS specific parts such as OS specific includes and function calls for timers and threads etc. This was done to enable RVCT compilation for profiling purposes or running the image on bare metal target with Lauterbach. Removed separate AREA directives for READONLY data in armv6 and neon assembly files to fix the RVCT compilation. Otherwise "ldr <reg>, =label" syntax would have been needed to prevent linker errors. This syntax is not supported by older gnu assemblers. Change-Id: I14f4c68529e8c27397502fbc3010a54e505ddb43
2011-01-24 10:21:40 +01:00
Initial WebM release
2010-05-18 17:58:33 +02:00
END
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