53 lines
2.2 KiB
Plaintext
53 lines
2.2 KiB
Plaintext
=pod
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=head1 NAME
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OPENSSL_ia32cap - finding the IA-32 processor capabilities
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=head1 SYNOPSIS
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unsigned int *OPENSSL_ia32cap_loc(void);
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#define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])
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=head1 DESCRIPTION
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Value returned by OPENSSL_ia32cap_loc() is address of a variable
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containing IA-32 processor capabilities bit vector as it appears in
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EDX:ECX register pair after executing CPUID instruction with EAX=1
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input value (see Intel Application Note #241618). Naturally it's
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meaningful on x86 and x86_64 platforms only. The variable is normally
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set up automatically upon toolkit initialization, but can be
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manipulated afterwards to modify crypto library behaviour. For the
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moment of this writing seven bits are significant, namely:
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1. bit #4 denoting presence of Time-Stamp Counter.
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2. bit #20, reserved by Intel, is used to choose among RC4 code
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paths;
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3. bit #23 denoting MMX support;
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4. bit #25 denoting SSE support;
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5. bit #26 denoting SSE2 support;
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6. bit #28 denoting Hyperthreading, which is used to distiguish
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cores with shared cache;
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7. bit #30, reserved by Intel, is used to choose among RC4 code
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paths;
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8. bit #57 denoting Intel AES instruction set extension;
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For example, clearing bit #26 at run-time disables high-performance
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SSE2 code present in the crypto library. You might have to do this if
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target OpenSSL application is executed on SSE2 capable CPU, but under
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control of OS which does not support SSE2 extentions. Even though you
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can manipulate the value programmatically, you most likely will find it
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more appropriate to set up an environment variable with the same name
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prior starting target application, e.g. on Intel P4 processor 'env
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OPENSSL_ia32cap=0x12900010 apps/openssl', to achieve same effect
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without modifying the application source code. Alternatively you can
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reconfigure the toolkit with no-sse2 option and recompile.
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Less intuituve is clearing bit #28. The truth is that it's not copied
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from CPUID output verbatim, but is adjusted to reflect whether or not
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the data cache is actually shared between logical cores. This in turn
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affects the decision on whether or not expensive countermeasures
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against cache-timing attacks are applied, most notably in AES assembler
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module.
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=cut
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