bsaes-armv7.pl: closest shave. While 0.3 cpb improvement on S4 appears
insignificant, it's actually 4 cycles less for 14 instructions sequence!
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@ -18,11 +18,13 @@
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# only low-level primitives and unsupported entry points, just enough
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# to collect performance results, which for Cortex-A8 core are:
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#
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# encrypt 19.7 cycles per byte processed with 128-bit key
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# decrypt 24.1 cycles per byte processed with 128-bit key
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# key conv. 440 cycles per 128-bit key/0.17 of 8x block
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# encrypt 19.5 cycles per byte processed with 128-bit key
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# decrypt 24.0 cycles per byte processed with 128-bit key
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# key conv. 440 cycles per 128-bit key/0.18 of 8x block
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#
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# Snapdragon S4 encrypts byte in 17.9 cycles and decrypts in 22.9.
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# Snapdragon S4 encrypts byte in 17.6 cycles and decrypts in 22.6,
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# which is [much] worse than anticipated (for further details see
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# http://www.openssl.org/~appro/Snapdragon-S4.html).
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#
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# When comparing to x86_64 results keep in mind that NEON unit is
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# [mostly] single-issue and thus can't [fully] benefit from
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@ -282,35 +284,32 @@ $code.=<<___;
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vand @s[2], @x[5], @x[1]
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vorr @s[3], @x[4], @x[0]
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veor @t[3], @t[3], @s[0]
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veor @t[2], @t[2], @s[1]
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veor @t[1], @t[1], @s[2]
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veor @t[0], @t[0], @s[3]
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veor @t[2], @t[2], @s[1]
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@ Inv_GF16 \t0, \t1, \t2, \t3, \s0, \s1, \s2, \s3
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@ new smaller inversion
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veor @s[0], @t[3], @t[2]
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vand @t[3], @t[3], @t[1]
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vand @s[2], @t[3], @t[1]
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vmov @s[0], @t[0]
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veor @s[2], @t[0], @t[3]
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veor @s[1], @t[2], @t[3]
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veor @s[1], @t[2], @s[2]
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veor @s[3], @t[0], @s[2]
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veor @s[2], @t[0], @s[2] @ @s[2]=@s[3]
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vand @s[3], @s[0], @s[2]
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vbsl @s[1], @t[1], @t[0]
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vbsl @s[3], @t[3], @t[2]
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veor @t[3], @t[3], @t[2]
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veor @s[3], @s[3], @t[2]
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veor @t[2], @s[2], @s[1]
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vand @t[2], @t[2], @t[0]
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vbsl @s[0], @s[1], @s[2]
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vbsl @t[0], @s[2], @s[1]
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veor @s[2], @s[2], @t[2]
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vand @s[2], @s[0], @s[3]
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veor @t[1], @t[1], @t[0]
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vand @s[2], @s[2], @s[3]
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veor @s[2], @s[2], @s[0]
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veor @s[2], @s[2], @t[3]
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___
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# output in s3, s2, s1, t1
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