vpaes-ppc.pl: comply with ABI.
This commit is contained in:
Andy Polyakov
parent
27da939490
commit
b83d09f552
@ -35,12 +35,14 @@ if ($flavour =~ /64/) {
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$STU ="stdu";
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$STU ="stdu";
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$POP ="ld";
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$POP ="ld";
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$PUSH ="std";
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$PUSH ="std";
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$UCMP ="cmpld";
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} elsif ($flavour =~ /32/) {
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} elsif ($flavour =~ /32/) {
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$SIZE_T =4;
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$SIZE_T =4;
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$LRSAVE =$SIZE_T;
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$LRSAVE =$SIZE_T;
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$STU ="stwu";
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$STU ="stwu";
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$POP ="lwz";
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$POP ="lwz";
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$PUSH ="stw";
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$PUSH ="stw";
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$UCMP ="cmplw";
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} else { die "nonsense $flavour"; }
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} else { die "nonsense $flavour"; }
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$sp="r1";
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$sp="r1";
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@ -302,28 +304,28 @@ Lenc_entry:
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mflr r6
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mflr r6
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mfspr r7, 256 # save vrsave
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mfspr r7, 256 # save vrsave
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stvx v20,r10,$sp
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stvx v20,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v21,r11,$sp
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stvx v21,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v22,r10,$sp
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stvx v22,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v23,r11,$sp
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stvx v23,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v24,r10,$sp
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stvx v24,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v25,r11,$sp
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stvx v25,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v26,r10,$sp
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stvx v26,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v27,r11,$sp
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stvx v27,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v28,r10,$sp
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stvx v28,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v29,r11,$sp
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stvx v29,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v30,r10,$sp
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stvx v30,r10,$sp
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stvx v31,r11,$sp
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stvx v31,r11,$sp
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lwz r7,`$FRAME-4`($sp) # save vrsave
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stw r7,`$FRAME-4`($sp) # save vrsave
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li r0, -1
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li r0, -1
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$PUSH r6,`$FRAME+$LRSAVE`($sp)
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$PUSH r6,`$FRAME+$LRSAVE`($sp)
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mtspr 256, r0 # preserve all AltiVec registers
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mtspr 256, r0 # preserve all AltiVec registers
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@ -359,25 +361,25 @@ Lenc_entry:
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mtlr r6
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mtlr r6
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mtspr 256, r7 # restore vrsave
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mtspr 256, r7 # restore vrsave
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lvx v20,r10,$sp
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lvx v20,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v21,r11,$sp
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lvx v21,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v22,r10,$sp
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lvx v22,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v23,r11,$sp
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lvx v23,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v24,r10,$sp
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lvx v24,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v25,r11,$sp
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lvx v25,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v26,r10,$sp
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lvx v26,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v27,r11,$sp
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lvx v27,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v28,r10,$sp
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lvx v28,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v29,r11,$sp
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lvx v29,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v30,r10,$sp
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lvx v30,r10,$sp
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lvx v31,r11,$sp
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lvx v31,r11,$sp
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addi $sp,$sp,$FRAME
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addi $sp,$sp,$FRAME
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@ -531,28 +533,28 @@ Ldec_entry:
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mflr r6
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mflr r6
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mfspr r7, 256 # save vrsave
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mfspr r7, 256 # save vrsave
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stvx v20,r10,$sp
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stvx v20,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v21,r11,$sp
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stvx v21,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v22,r10,$sp
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stvx v22,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v23,r11,$sp
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stvx v23,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v24,r10,$sp
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stvx v24,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v25,r11,$sp
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stvx v25,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v26,r10,$sp
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stvx v26,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v27,r11,$sp
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stvx v27,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v28,r10,$sp
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stvx v28,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v29,r11,$sp
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stvx v29,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v30,r10,$sp
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stvx v30,r10,$sp
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stvx v31,r11,$sp
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stvx v31,r11,$sp
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lwz r7,`$FRAME-4`($sp) # save vrsave
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stw r7,`$FRAME-4`($sp) # save vrsave
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li r0, -1
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li r0, -1
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$PUSH r6,`$FRAME+$LRSAVE`($sp)
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$PUSH r6,`$FRAME+$LRSAVE`($sp)
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mtspr 256, r0 # preserve all AltiVec registers
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mtspr 256, r0 # preserve all AltiVec registers
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@ -588,25 +590,25 @@ Ldec_entry:
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mtlr r6
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mtlr r6
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mtspr 256, r7 # restore vrsave
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mtspr 256, r7 # restore vrsave
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lvx v20,r10,$sp
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lvx v20,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v21,r11,$sp
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lvx v21,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v22,r10,$sp
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lvx v22,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v23,r11,$sp
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lvx v23,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v24,r10,$sp
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lvx v24,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v25,r11,$sp
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lvx v25,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v26,r10,$sp
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lvx v26,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v27,r11,$sp
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lvx v27,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v28,r10,$sp
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lvx v28,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v29,r11,$sp
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lvx v29,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v30,r10,$sp
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lvx v30,r10,$sp
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lvx v31,r11,$sp
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lvx v31,r11,$sp
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addi $sp,$sp,$FRAME
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addi $sp,$sp,$FRAME
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@ -619,40 +621,43 @@ Ldec_entry:
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.globl .vpaes_cbc_encrypt
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.globl .vpaes_cbc_encrypt
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.align 5
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.align 5
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.vpaes_cbc_encrypt:
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.vpaes_cbc_encrypt:
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${UCMP}i r5,16
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bltlr-
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$STU $sp,-`($FRAME+2*$SIZE_T)`($sp)
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$STU $sp,-`($FRAME+2*$SIZE_T)`($sp)
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mflr r0
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mflr r0
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li r10,`15+6*$SIZE_T`
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li r10,`15+6*$SIZE_T`
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li r11,`31+6*$SIZE_T`
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li r11,`31+6*$SIZE_T`
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mfspr r12, 256
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mfspr r12, 256
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stvx v20,r10,$sp
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stvx v20,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v21,r11,$sp
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stvx v21,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v22,r10,$sp
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stvx v22,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v23,r11,$sp
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stvx v23,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v24,r10,$sp
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stvx v24,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v25,r11,$sp
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stvx v25,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v26,r10,$sp
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stvx v26,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v27,r11,$sp
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stvx v27,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v28,r10,$sp
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stvx v28,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v29,r11,$sp
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stvx v29,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v30,r10,$sp
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stvx v30,r10,$sp
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stvx v31,r11,$sp
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stvx v31,r11,$sp
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lwz r12,`$FRAME-4`($sp) # save vrsave
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stw r12,`$FRAME-4`($sp) # save vrsave
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$PUSH r30,`$FRAME+$SIZE_T*0`($sp)
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$PUSH r30,`$FRAME+$SIZE_T*0`($sp)
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$PUSH r31,`$FRAME+$SIZE_T*1`($sp)
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$PUSH r31,`$FRAME+$SIZE_T*1`($sp)
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li r9, 16
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li r9, -16
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$PUSH r0, `$FRAME+$SIZE_T*2+$LRSAVE`($sp)
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$PUSH r0, `$FRAME+$SIZE_T*2+$LRSAVE`($sp)
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sub. r30, r5, r9 # copy length-16
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and r30, r5, r9 # copy length&-16
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mr r5, r6 # copy pointer to key
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mr r5, r6 # copy pointer to key
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mr r31, r7 # copy pointer to iv
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mr r31, r7 # copy pointer to iv
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blt Lcbc_abort
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blt Lcbc_abort
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@ -699,7 +704,7 @@ Lcbc_enc_loop:
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vmr $outhead, v0
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vmr $outhead, v0
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stvx v1, 0, $out
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stvx v1, 0, $out
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addi $out, $out, 16
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addi $out, $out, 16
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bge Lcbc_enc_loop
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bne Lcbc_enc_loop
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b Lcbc_done
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b Lcbc_done
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@ -725,7 +730,7 @@ Lcbc_dec_loop:
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vmr $outhead, v0
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vmr $outhead, v0
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stvx v1, 0, $out
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stvx v1, 0, $out
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addi $out, $out, 16
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addi $out, $out, 16
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bge Lcbc_dec_loop
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bne Lcbc_dec_loop
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Lcbc_done:
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Lcbc_done:
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addi $out, $out, -1
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addi $out, $out, -1
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@ -750,25 +755,25 @@ Lcbc_done:
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li r10,`15+6*$SIZE_T`
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li r10,`15+6*$SIZE_T`
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li r11,`31+6*$SIZE_T`
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li r11,`31+6*$SIZE_T`
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lvx v20,r10,$sp
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lvx v20,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v21,r11,$sp
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lvx v21,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v22,r10,$sp
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lvx v22,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v23,r11,$sp
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lvx v23,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v24,r10,$sp
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lvx v24,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v25,r11,$sp
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lvx v25,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v26,r10,$sp
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lvx v26,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v27,r11,$sp
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lvx v27,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v28,r10,$sp
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lvx v28,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v29,r11,$sp
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lvx v29,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v30,r10,$sp
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lvx v30,r10,$sp
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lvx v31,r11,$sp
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lvx v31,r11,$sp
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Lcbc_abort:
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Lcbc_abort:
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@ -1306,28 +1311,28 @@ Lschedule_mangle_dec:
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mflr r0
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mflr r0
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mfspr r6, 256 # save vrsave
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mfspr r6, 256 # save vrsave
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stvx v20,r10,$sp
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stvx v20,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v21,r11,$sp
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stvx v21,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v22,r10,$sp
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stvx v22,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v23,r11,$sp
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stvx v23,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v24,r10,$sp
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stvx v24,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v25,r11,$sp
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stvx v25,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v26,r10,$sp
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stvx v26,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v27,r11,$sp
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stvx v27,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v28,r10,$sp
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stvx v28,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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stvx v29,r11,$sp
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stvx v29,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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stvx v30,r10,$sp
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stvx v30,r10,$sp
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stvx v31,r11,$sp
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stvx v31,r11,$sp
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lwz r6,`$FRAME-4`($sp) # save vrsave
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stw r6,`$FRAME-4`($sp) # save vrsave
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li r7, -1
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li r7, -1
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$PUSH r0, `$FRAME+$LRSAVE`($sp)
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$PUSH r0, `$FRAME+$LRSAVE`($sp)
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mtspr 256, r7 # preserve all AltiVec registers
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mtspr 256, r7 # preserve all AltiVec registers
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@ -1347,25 +1352,25 @@ Lschedule_mangle_dec:
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mtlr r0
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mtlr r0
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xor r3, r3, r3
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xor r3, r3, r3
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lvx v20,r10,$sp
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lvx v20,r10,$sp
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addi r10,r10,16
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addi r10,r10,32
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lvx v21,r11,$sp
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lvx v21,r11,$sp
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addi r11,r11,16
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addi r11,r11,32
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lvx v22,r10,$sp
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lvx v22,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
lvx v23,r11,$sp
|
lvx v23,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
lvx v24,r10,$sp
|
lvx v24,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
lvx v25,r11,$sp
|
lvx v25,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
lvx v26,r10,$sp
|
lvx v26,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
lvx v27,r11,$sp
|
lvx v27,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
lvx v28,r10,$sp
|
lvx v28,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
lvx v29,r11,$sp
|
lvx v29,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
lvx v30,r10,$sp
|
lvx v30,r10,$sp
|
||||||
lvx v31,r11,$sp
|
lvx v31,r11,$sp
|
||||||
addi $sp,$sp,$FRAME
|
addi $sp,$sp,$FRAME
|
||||||
@ -1384,28 +1389,28 @@ Lschedule_mangle_dec:
|
|||||||
mflr r0
|
mflr r0
|
||||||
mfspr r6, 256 # save vrsave
|
mfspr r6, 256 # save vrsave
|
||||||
stvx v20,r10,$sp
|
stvx v20,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
stvx v21,r11,$sp
|
stvx v21,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
stvx v22,r10,$sp
|
stvx v22,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
stvx v23,r11,$sp
|
stvx v23,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
stvx v24,r10,$sp
|
stvx v24,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
stvx v25,r11,$sp
|
stvx v25,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
stvx v26,r10,$sp
|
stvx v26,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
stvx v27,r11,$sp
|
stvx v27,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
stvx v28,r10,$sp
|
stvx v28,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
stvx v29,r11,$sp
|
stvx v29,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
stvx v30,r10,$sp
|
stvx v30,r10,$sp
|
||||||
stvx v31,r11,$sp
|
stvx v31,r11,$sp
|
||||||
lwz r6,`$FRAME-4`($sp) # save vrsave
|
stw r6,`$FRAME-4`($sp) # save vrsave
|
||||||
li r7, -1
|
li r7, -1
|
||||||
$PUSH r0, `$FRAME+$LRSAVE`($sp)
|
$PUSH r0, `$FRAME+$LRSAVE`($sp)
|
||||||
mtspr 256, r7 # preserve all AltiVec registers
|
mtspr 256, r7 # preserve all AltiVec registers
|
||||||
@ -1430,25 +1435,25 @@ Lschedule_mangle_dec:
|
|||||||
mtlr r0
|
mtlr r0
|
||||||
xor r3, r3, r3
|
xor r3, r3, r3
|
||||||
lvx v20,r10,$sp
|
lvx v20,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
lvx v21,r11,$sp
|
lvx v21,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
lvx v22,r10,$sp
|
lvx v22,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
lvx v23,r11,$sp
|
lvx v23,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
lvx v24,r10,$sp
|
lvx v24,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
lvx v25,r11,$sp
|
lvx v25,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
lvx v26,r10,$sp
|
lvx v26,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
lvx v27,r11,$sp
|
lvx v27,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
lvx v28,r10,$sp
|
lvx v28,r10,$sp
|
||||||
addi r10,r10,16
|
addi r10,r10,32
|
||||||
lvx v29,r11,$sp
|
lvx v29,r11,$sp
|
||||||
addi r11,r11,16
|
addi r11,r11,32
|
||||||
lvx v30,r10,$sp
|
lvx v30,r10,$sp
|
||||||
lvx v31,r11,$sp
|
lvx v31,r11,$sp
|
||||||
addi $sp,$sp,$FRAME
|
addi $sp,$sp,$FRAME
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user