crypto/bn/rsaz*: fix licensing note.
rsaz_exp.c: harmonize line terminating; asm/rsaz-*.pl: minor optimizations. asm/rsaz-x86_64.pl: sync from master. (cherry picked from commit 31ed9a21315c571db443c68e4f618ecb51c631f9)
This commit is contained in:
Andy Polyakov
parent
36982f056a
commit
87d9526d0c
@ -1,54 +1,66 @@
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#!/usr/bin/env perl
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#******************************************************************************
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#* Copyright(c) 2012, Intel Corp.
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#* Developers and authors:
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#* Shay Gueron (1, 2), and Vlad Krasnov (1)
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#* (1) Intel Corporation, Israel Development Center, Haifa, Israel
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#* (2) University of Haifa, Israel
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#******************************************************************************
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#* LICENSE:
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#* This submission to OpenSSL is to be made available under the OpenSSL
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#* license, and only to the OpenSSL project, in order to allow integration
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#* into the publicly distributed code.
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#* The use of this code, or portions of this code, or concepts embedded in
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#* this code, or modification of this code and/or algorithm(s) in it, or the
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#* use of this code for any other purpose than stated above, requires special
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#* licensing.
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#******************************************************************************
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#* DISCLAIMER:
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#* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS AND THE COPYRIGHT OWNERS
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#* ``AS IS''. ANY EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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#* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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#* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE CONTRIBUTORS OR THE COPYRIGHT
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#* OWNERS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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#* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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#* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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#* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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#* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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#* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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#* POSSIBILITY OF SUCH DAMAGE.
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#******************************************************************************
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#* Reference:
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#* [1] S. Gueron, V. Krasnov: "Software Implementation of Modular
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#* Exponentiation, Using Advanced Vector Instructions Architectures",
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#* F. Ozbudak and F. Rodriguez-Henriquez (Eds.): WAIFI 2012, LNCS 7369,
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#* pp. 119?135, 2012. Springer-Verlag Berlin Heidelberg 2012
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#* [2] S. Gueron: "Efficient Software Implementations of Modular
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#* Exponentiation", Journal of Cryptographic Engineering 2:31-43 (2012).
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#* [3] S. Gueron, V. Krasnov: "Speeding up Big-numbers Squaring",IEEE
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#* Proceedings of 9th International Conference on Information Technology:
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#* New Generations (ITNG 2012), pp.821-823 (2012)
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#* [4] S. Gueron, V. Krasnov: "[PATCH] Efficient and side channel analysis
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#* resistant 1024-bit modular exponentiation, for optimizing RSA2048
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#* on AVX2 capable x86_64 platforms",
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#* http://rt.openssl.org/Ticket/Display.html?id=2850&user=guest&pass=guest
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#******************************************************************************
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# +10% improvement by <appro@openssl.org>
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##############################################################################
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# #
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# Copyright (c) 2012, Intel Corporation #
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# #
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# All rights reserved. #
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# #
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# Redistribution and use in source and binary forms, with or without #
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# modification, are permitted provided that the following conditions are #
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# met: #
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# #
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# * Redistributions of source code must retain the above copyright #
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# notice, this list of conditions and the following disclaimer. #
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# #
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# * Redistributions in binary form must reproduce the above copyright #
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# notice, this list of conditions and the following disclaimer in the #
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# documentation and/or other materials provided with the #
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# distribution. #
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# #
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# * Neither the name of the Intel Corporation nor the names of its #
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# contributors may be used to endorse or promote products derived from #
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# this software without specific prior written permission. #
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# #
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# #
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# THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY #
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# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE #
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR #
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# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR #
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# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
|
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, #
|
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# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR #
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# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF #
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# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS #
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# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #
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# #
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##############################################################################
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# Developers and authors: #
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# Shay Gueron (1, 2), and Vlad Krasnov (1) #
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# (1) Intel Corporation, Israel Development Center, Haifa, Israel #
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# (2) University of Haifa, Israel #
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##############################################################################
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# Reference: #
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# [1] S. Gueron, V. Krasnov: "Software Implementation of Modular #
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# Exponentiation, Using Advanced Vector Instructions Architectures", #
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# F. Ozbudak and F. Rodriguez-Henriquez (Eds.): WAIFI 2012, LNCS 7369, #
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# pp. 119?135, 2012. Springer-Verlag Berlin Heidelberg 2012 #
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# [2] S. Gueron: "Efficient Software Implementations of Modular #
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# Exponentiation", Journal of Cryptographic Engineering 2:31-43 (2012). #
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# [3] S. Gueron, V. Krasnov: "Speeding up Big-numbers Squaring",IEEE #
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# Proceedings of 9th International Conference on Information Technology: #
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# New Generations (ITNG 2012), pp.821-823 (2012) #
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# [4] S. Gueron, V. Krasnov: "[PATCH] Efficient and side channel analysis #
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# resistant 1024-bit modular exponentiation, for optimizing RSA2048 #
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# on AVX2 capable x86_64 platforms", #
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# http://rt.openssl.org/Ticket/Display.html?id=2850&user=guest&pass=guest#
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##############################################################################
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#
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# +13% improvement over original submission by <appro@openssl.org>
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#
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# rsa2048 sign/sec OpenSSL 1.0.1 scalar(*) this
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# 2.3GHz Haswell 621 732/+18% 1112/+79%
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# 2.3GHz Haswell 621 765/+23% 1113/+79%
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#
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# (*) if system doesn't support AVX2, for reference purposes;
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@ -143,24 +155,24 @@ rsaz_1024_sqr_avx2: # 702 cycles, 14% faster than rsaz_1024_mul_avx2
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push %r13
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push %r14
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push %r15
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vzeroupper
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___
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$code.=<<___ if ($win64);
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lea -0xa8(%rsp),%rsp
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movaps %xmm6,-0xd8(%rax)
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movaps %xmm7,-0xc8(%rax)
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movaps %xmm8,-0xb8(%rax)
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movaps %xmm9,-0xa8(%rax)
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movaps %xmm10,-0x98(%rax)
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movaps %xmm11,-0x88(%rax)
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movaps %xmm12,-0x78(%rax)
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movaps %xmm13,-0x68(%rax)
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movaps %xmm14,-0x58(%rax)
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movaps %xmm15,-0x48(%rax)
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vmovaps %xmm6,-0xd8(%rax)
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vmovaps %xmm7,-0xc8(%rax)
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vmovaps %xmm8,-0xb8(%rax)
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vmovaps %xmm9,-0xa8(%rax)
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vmovaps %xmm10,-0x98(%rax)
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vmovaps %xmm11,-0x88(%rax)
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vmovaps %xmm12,-0x78(%rax)
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vmovaps %xmm13,-0x68(%rax)
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vmovaps %xmm14,-0x58(%rax)
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vmovaps %xmm15,-0x48(%rax)
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.Lsqr_1024_body:
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___
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$code.=<<___;
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mov %rax,%rbp
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vzeroall
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mov %rdx, $np # reassigned argument
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sub \$$FrameSize, %rsp
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mov $np, $tmp
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@ -171,6 +183,7 @@ $code.=<<___;
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and \$4095, $tmp # see if $np crosses page
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add \$32*10, $tmp
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shr \$12, $tmp
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vpxor $ACC9,$ACC9,$ACC9
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jz .Lsqr_1024_no_n_copy
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# unaligned 256-bit load that crosses page boundary can
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@ -198,7 +211,7 @@ $code.=<<___;
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vmovdqu $ACC6, 32*6-128($np)
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vmovdqu $ACC7, 32*7-128($np)
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vmovdqu $ACC8, 32*8-128($np)
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vmovdqu $ACC9, 32*9-128($np) # $ACC9 is zero after vzeroall
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vmovdqu $ACC9, 32*9-128($np) # $ACC9 is zero
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.Lsqr_1024_no_n_copy:
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and \$-1024, %rsp
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@ -876,17 +889,18 @@ rsaz_1024_mul_avx2:
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push %r15
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___
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$code.=<<___ if ($win64);
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vzeroupper
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lea -0xa8(%rsp),%rsp
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movaps %xmm6,-0xd8(%rax)
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movaps %xmm7,-0xc8(%rax)
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movaps %xmm8,-0xb8(%rax)
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movaps %xmm9,-0xa8(%rax)
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movaps %xmm10,-0x98(%rax)
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movaps %xmm11,-0x88(%rax)
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movaps %xmm12,-0x78(%rax)
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movaps %xmm13,-0x68(%rax)
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movaps %xmm14,-0x58(%rax)
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movaps %xmm15,-0x48(%rax)
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vmovaps %xmm6,-0xd8(%rax)
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vmovaps %xmm7,-0xc8(%rax)
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vmovaps %xmm8,-0xb8(%rax)
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vmovaps %xmm9,-0xa8(%rax)
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vmovaps %xmm10,-0x98(%rax)
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vmovaps %xmm11,-0x88(%rax)
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vmovaps %xmm12,-0x78(%rax)
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vmovaps %xmm13,-0x68(%rax)
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vmovaps %xmm14,-0x58(%rax)
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vmovaps %xmm15,-0x48(%rax)
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.Lmul_1024_body:
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___
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$code.=<<___;
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@ -900,6 +914,7 @@ $code.=<<___;
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# cross page boundary, swap it with $bp [meaning that caller
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# is advised to lay down $ap and $bp next to each other, so
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# that only one can cross page boundary].
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.byte 0x67,0x67
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mov $ap, $tmp
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and \$4095, $tmp
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add \$32*10, $tmp
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@ -915,6 +930,7 @@ $code.=<<___;
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and \$4095, $tmp # see if $np crosses page
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add \$32*10, $tmp
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.byte 0x67,0x67
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shr \$12, $tmp
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jz .Lmul_1024_no_n_copy
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@ -960,6 +976,7 @@ $code.=<<___;
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vpbroadcastq ($bp), $Bi
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vmovdqu $ACC0, (%rsp) # clear top of stack
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xor $r0, $r0
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.byte 0x67
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xor $r1, $r1
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xor $r2, $r2
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xor $r3, $r3
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@ -1564,22 +1581,22 @@ rsaz_1024_gather5_avx2:
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___
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$code.=<<___ if ($win64);
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lea -0x88(%rsp),%rax
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vzeroupper
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.LSEH_begin_rsaz_1024_gather5:
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# I can't trust assembler to use specific encoding:-(
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.byte 0x48,0x8d,0x60,0xe0 #lea -0x20(%rax),%rsp
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.byte 0x0f,0x29,0x70,0xe0 #movaps %xmm6,-0x20(%rax)
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.byte 0x0f,0x29,0x78,0xf0 #movaps %xmm7,-0x10(%rax)
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.byte 0x44,0x0f,0x29,0x00 #movaps %xmm8,0(%rax)
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.byte 0x44,0x0f,0x29,0x48,0x10 #movaps %xmm9,0x10(%rax)
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.byte 0x44,0x0f,0x29,0x50,0x20 #movaps %xmm10,0x20(%rax)
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.byte 0x44,0x0f,0x29,0x58,0x30 #movaps %xmm11,0x30(%rax)
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.byte 0x44,0x0f,0x29,0x60,0x40 #movaps %xmm12,0x40(%rax)
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.byte 0x44,0x0f,0x29,0x68,0x50 #movaps %xmm13,0x50(%rax)
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.byte 0x44,0x0f,0x29,0x70,0x60 #movaps %xmm14,0x60(%rax)
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.byte 0x44,0x0f,0x29,0x78,0x70 #movaps %xmm15,0x70(%rax)
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.byte 0xc5,0xf8,0x29,0x70,0xe0 #vmovaps %xmm6,-0x20(%rax)
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.byte 0xc5,0xf8,0x29,0x78,0xf0 #vmovaps %xmm7,-0x10(%rax)
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.byte 0xc5,0x78,0x29,0x40,0x00 #vmovaps %xmm8,0(%rax)
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.byte 0xc5,0x78,0x29,0x48,0x10 #vmovaps %xmm9,0x10(%rax)
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.byte 0xc5,0x78,0x29,0x50,0x20 #vmovaps %xmm10,0x20(%rax)
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.byte 0xc5,0x78,0x29,0x58,0x30 #vmovaps %xmm11,0x30(%rax)
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.byte 0xc5,0x78,0x29,0x60,0x40 #vmovaps %xmm12,0x40(%rax)
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.byte 0xc5,0x78,0x29,0x68,0x50 #vmovaps %xmm13,0x50(%rax)
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.byte 0xc5,0x78,0x29,0x70,0x60 #vmovaps %xmm14,0x60(%rax)
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.byte 0xc5,0x78,0x29,0x78,0x70 #vmovaps %xmm15,0x70(%rax)
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___
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$code.=<<___;
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vzeroupper
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lea .Lgather_table(%rip),%r11
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mov $power,%eax
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and \$3,$power
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@ -1596,25 +1613,25 @@ $code.=<<___;
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vpbroadcastb 2(%r11,%rax), %xmm14
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vpbroadcastb 1(%r11,%rax), %xmm15
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lea ($inp,$power),$inp
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lea 64($inp,$power),$inp
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mov \$64,%r11 # size optimization
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mov \$9,%eax
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jmp .Loop_gather_1024
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.align 32
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.Loop_gather_1024:
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vpand ($inp), %xmm8,%xmm0
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vpand ($inp,%r11), %xmm9,%xmm1
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vpand ($inp,%r11,2), %xmm10,%xmm2
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vpand 64($inp,%r11,2), %xmm11,%xmm3
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vpand -64($inp), %xmm8,%xmm0
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vpand ($inp), %xmm9,%xmm1
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vpand 64($inp), %xmm10,%xmm2
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vpand ($inp,%r11,2), %xmm11,%xmm3
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vpor %xmm0,%xmm1,%xmm1
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vpand ($inp,%r11,4), %xmm12,%xmm4
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vpand 64($inp,%r11,2), %xmm12,%xmm4
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vpor %xmm2,%xmm3,%xmm3
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vpand 64($inp,%r11,4), %xmm13,%xmm5
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vpand ($inp,%r11,4), %xmm13,%xmm5
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vpor %xmm1,%xmm3,%xmm3
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vpand -128($inp,%r11,8), %xmm14,%xmm6
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vpand 64($inp,%r11,4), %xmm14,%xmm6
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vpor %xmm4,%xmm5,%xmm5
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vpand -64($inp,%r11,8), %xmm15,%xmm2
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vpand -128($inp,%r11,8), %xmm15,%xmm2
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lea ($inp,%r11,8),$inp
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vpor %xmm3,%xmm5,%xmm5
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vpor %xmm2,%xmm6,%xmm6
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@ -1798,16 +1815,16 @@ rsaz_se_handler:
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.rva .Lmul_1024_body,.Lmul_1024_epilogue
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.LSEH_info_rsaz_1024_gather5:
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.byte 0x01,0x33,0x16,0x00
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.byte 0x33,0xf8,0x09,0x00 #movaps 0x90(rsp),xmm15
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.byte 0x2e,0xe8,0x08,0x00 #movaps 0x80(rsp),xmm14
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.byte 0x29,0xd8,0x07,0x00 #movaps 0x70(rsp),xmm13
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.byte 0x24,0xc8,0x06,0x00 #movaps 0x60(rsp),xmm12
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.byte 0x1f,0xb8,0x05,0x00 #movaps 0x50(rsp),xmm11
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.byte 0x1a,0xa8,0x04,0x00 #movaps 0x40(rsp),xmm10
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.byte 0x15,0x98,0x03,0x00 #movaps 0x30(rsp),xmm9
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.byte 0x10,0x88,0x02,0x00 #movaps 0x20(rsp),xmm8
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.byte 0x0c,0x78,0x01,0x00 #movaps 0x10(rsp),xmm7
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.byte 0x08,0x68,0x00,0x00 #movaps 0x00(rsp),xmm6
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.byte 0x36,0xf8,0x09,0x00 #vmovaps 0x90(rsp),xmm15
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.byte 0x31,0xe8,0x08,0x00 #vmovaps 0x80(rsp),xmm14
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.byte 0x2c,0xd8,0x07,0x00 #vmovaps 0x70(rsp),xmm13
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.byte 0x27,0xc8,0x06,0x00 #vmovaps 0x60(rsp),xmm12
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.byte 0x22,0xb8,0x05,0x00 #vmovaps 0x50(rsp),xmm11
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.byte 0x1d,0xa8,0x04,0x00 #vmovaps 0x40(rsp),xmm10
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.byte 0x18,0x98,0x03,0x00 #vmovaps 0x30(rsp),xmm9
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.byte 0x13,0x88,0x02,0x00 #vmovaps 0x20(rsp),xmm8
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.byte 0x0e,0x78,0x01,0x00 #vmovaps 0x10(rsp),xmm7
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.byte 0x09,0x68,0x00,0x00 #vmovaps 0x00(rsp),xmm6
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.byte 0x04,0x01,0x15,0x00 #sub rsp,0xa8
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___
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}
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File diff suppressed because it is too large
Load Diff
@ -1,32 +1,44 @@
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/******************************************************************************
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* Copyright(c) 2012, Intel Corp.
|
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* Developers and authors:
|
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* Shay Gueron (1, 2), and Vlad Krasnov (1)
|
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* (1) Intel Corporation, Israel Development Center, Haifa, Israel
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* (2) University of Haifa, Israel
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/*****************************************************************************
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* *
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* Copyright (c) 2012, Intel Corporation *
|
||||
* *
|
||||
* All rights reserved. *
|
||||
* *
|
||||
* Redistribution and use in source and binary forms, with or without *
|
||||
* modification, are permitted provided that the following conditions are *
|
||||
* met: *
|
||||
* *
|
||||
* * Redistributions of source code must retain the above copyright *
|
||||
* notice, this list of conditions and the following disclaimer. *
|
||||
* *
|
||||
* * Redistributions in binary form must reproduce the above copyright *
|
||||
* notice, this list of conditions and the following disclaimer in the *
|
||||
* documentation and/or other materials provided with the *
|
||||
* distribution. *
|
||||
* *
|
||||
* * Neither the name of the Intel Corporation nor the names of its *
|
||||
* contributors may be used to endorse or promote products derived from *
|
||||
* this software without specific prior written permission. *
|
||||
* *
|
||||
* *
|
||||
* THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY *
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR *
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR *
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, *
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR *
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF *
|
||||
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING *
|
||||
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS *
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
|
||||
* *
|
||||
******************************************************************************
|
||||
* LICENSE:
|
||||
* This submission to OpenSSL is to be made available under the OpenSSL
|
||||
* license, and only to the OpenSSL project, in order to allow integration
|
||||
* into the publicly distributed code.
|
||||
* The use of this code, or portions of this code, or concepts embedded in
|
||||
* this code, or modification of this code and/or algorithm(s) in it, or the
|
||||
* use of this code for any other purpose than stated above, requires special
|
||||
* licensing.
|
||||
******************************************************************************
|
||||
* DISCLAIMER:
|
||||
* THIS SOFTWARE IS PROVIDED BY THE CONTRIBUTORS AND THE COPYRIGHT OWNERS
|
||||
* ``AS IS''. ANY EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
|
||||
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE CONTRIBUTORS OR THE COPYRIGHT
|
||||
* OWNERS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
|
||||
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
******************************************************************************/
|
||||
* Developers and authors: *
|
||||
* Shay Gueron (1, 2), and Vlad Krasnov (1) *
|
||||
* (1) Intel Corporation, Israel Development Center, Haifa, Israel *
|
||||
* (2) University of Haifa, Israel *
|
||||
*****************************************************************************/
|
||||
|
||||
#include "rsaz_exp.h"
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user